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描述RTL2GDS ASIC流程help,very important for the first time to touch asic back end flow
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Copyright © 2007 by Lee Eng Han.
All rights reserved. No portion of this book may be resold without the
written permission of the author.
For queries about permission to reproduce selections from this book,
please send an e-mail to Eng Han at pnr@eda-utilities.com.
Visit www.eda-utilities.com for information about this book.
ii
Table of Contents
Version 1.0
1. A Quick Tour from Gate to Layout ............................. 1
Step 1 Load Library .................................................................. 2
Step 2 Import Gate Netlist ........................................................ 5
Step 3 Specify Design Constraint .............................................. 8
Step 4 Floor Planning .............................................................. 10
Step 5 Power Planning .............................................................14
Step 6 Physical Synthesis .........................................................16
Step 7 Clock Tree Synthesis ................................................... 19
Step 8 Routing ......................................................................... 23
Step 9 Physical Verification .....................................................26
Step 10 Post-Layout Verification ...............................................28
Summary .................................................................................... 29
Chapter 1
A Quick Tourfr om Gates to
Layout
If you have no prior knowledge of Place and Route (P&R), this chapter
is designed to bootstrap you into the design of digital layout. Later in the
book, you will be able to master the rest of the materials. This chapter
covers the essential steps of a Gate to Layout flow. The details of the
flow will be addressed in subsequent chapters. If you are experienced in
P&R, you still might want to browse through this chapter to get a feel
for the technical aspects covered in the other chapters.
The basic steps of a Gate to Layout flow include the following:
Step 1 Load library
Step 2 Import gate netlist
Step 3 Specify design constraints
Step 4 Floor planning
Step 5 Power planning
Step 6 Physical synthesis
Step 7 Clock tree synthesis
Step 8 Routing
Step 9 Physical verification
Step 10 Post-layout verification
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