KL81 Sub-Family Reference Manual
Supports: MKL81Z128VMC7(R), MKL81Z128VLK7(R),
MKL81Z128VLL7(R), MKL81Z128VLH7(R), MKL81Z128VMP7(R)
Document Number: KL81P121M72SF0RM
Rev. 1, August 2015
Preliminary
Non-Disclosure Agreement required
KL81 Sub-Family Reference Manual, Rev. 1, August 2015
2
Preliminary
Freescale Semiconductor, Inc.
Non-Disclosure Agreement required
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................53
1.1.1 Purpose.........................................................................................................................................................53
1.1.2 Audience...................................................................................................................................................... 53
1.2 Conventions.................................................................................................................................................................. 53
1.2.1 Numbering systems......................................................................................................................................53
1.2.2 Typographic notation................................................................................................................................... 54
1.2.3 Special terms................................................................................................................................................54
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................55
2.2 Block diagram...............................................................................................................................................................55
2.3 Module functional categories........................................................................................................................................56
2.3.1 ARM® Cortex®-M0+ Core Modules..........................................................................................................58
2.3.2 System modules........................................................................................................................................... 58
2.3.3 Memories and memory interfaces................................................................................................................59
2.3.4 Clocks...........................................................................................................................................................60
2.3.5 Analog modules........................................................................................................................................... 60
2.3.6 Timer modules............................................................................................................................................. 61
2.3.7 Security and Integrity modules.................................................................................................................... 61
2.3.8 Communication interfaces........................................................................................................................... 62
2.3.9 Human-machine interfaces.......................................................................................................................... 62
Chapter 3
Core Overview
3.1 ARM Cortex-M0+ Core................................................................................................................................................65
3.1.1 Buses, interconnects, and interfaces............................................................................................................ 65
3.1.2 System tick timer......................................................................................................................................... 65
KL81 Sub-Family Reference Manual, Rev. 1, August 2015
Freescale Semiconductor, Inc.
Preliminary
3
Non-Disclosure Agreement required
Section number Title Page
3.1.3 Debug facilities............................................................................................................................................ 65
3.1.4 Core privilege levels.................................................................................................................................... 66
3.2 Nested vectored interrupt controller (NVIC) configuration......................................................................................... 66
3.2.1 Interrupt priority levels................................................................................................................................ 66
3.2.2 Non-maskable interrupt................................................................................................................................66
3.2.3 Interrupt connections....................................................................................................................................66
3.2.4 Interrupt channel assignments......................................................................................................................68
3.2.5 INTMUX0 input mux assignment............................................................................................................... 69
3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................................ 70
3.3.1 AWIC overview........................................................................................................................................... 70
3.3.2 Wake-up sources..........................................................................................................................................71
Chapter 4
Memories and Memory Interfaces
4.1 Flash memory............................................................................................................................................................... 73
4.1.1 Flash security............................................................................................................................................... 73
4.1.2 Flash modes..................................................................................................................................................73
4.1.3 Erase all flash contents.................................................................................................................................73
4.1.4 FTFA_FOPT register................................................................................................................................... 73
4.1.5 Flash access control introduction.................................................................................................................74
4.2 SRAM........................................................................................................................................................................... 74
4.2.1 SRAM sizes..................................................................................................................................................74
4.2.2 SRAM retention in low power modes..........................................................................................................75
4.3 System register file....................................................................................................................................................... 75
4.4 VBAT register file........................................................................................................................................................ 76
4.5 Memory map.................................................................................................................................................................76
4.5.1 Introduction..................................................................................................................................................76
4.5.2 System memory map....................................................................................................................................76
4.5.3 Flash memory map.......................................................................................................................................79
4.5.4 SRAM memory map.................................................................................................................................... 80
KL81 Sub-Family Reference Manual, Rev. 1, August 2015
4
Preliminary
Freescale Semiconductor, Inc.
Non-Disclosure Agreement required
Section number Title Page
4.5.5 Peripheral bridge (AIPS-Lite) memory map................................................................................................80
4.5.6 Private peripherals........................................................................................................................................84
4.5.7 Private peripheral bus (PPB) memory map..................................................................................................85
Chapter 5
Clock Distribution using MCG
5.1 Introduction...................................................................................................................................................................87
5.2 Programming model......................................................................................................................................................87
5.3 High-Level device clocking diagram............................................................................................................................87
5.4 Clock definitions...........................................................................................................................................................88
5.4.1 Device clock summary.................................................................................................................................89
5.5 Internal clocking requirements..................................................................................................................................... 92
5.5.1 Clock divider values after reset....................................................................................................................92
5.5.2 VLPR mode clocking...................................................................................................................................93
5.6 Clock gating..................................................................................................................................................................93
5.7 Module clocks...............................................................................................................................................................94
5.7.1 PMC 1-kHz LPO clock................................................................................................................................95
5.7.2 IRC 48MHz clock........................................................................................................................................ 95
5.7.3 WDOG clocking.......................................................................................................................................... 96
5.7.4 PORT digital filter clocking.........................................................................................................................97
5.7.5 LPTMR clocking..........................................................................................................................................97
5.7.6 TPM clocking...............................................................................................................................................98
5.7.7 USB FS OTG Controller clocking...............................................................................................................98
5.7.8 LPUART clocking....................................................................................................................................... 99
5.7.9 QSPI clocking.............................................................................................................................................. 99
5.7.10 LP Trusted Cryptography (LTC) clocking...................................................................................................100
5.7.11 TRNG clocking............................................................................................................................................100
5.7.12 FlexIO clocking............................................................................................................................................100
5.7.13 EMVSIM clocking.......................................................................................................................................101
KL81 Sub-Family Reference Manual, Rev. 1, August 2015
Freescale Semiconductor, Inc.
Preliminary
5
Non-Disclosure Agreement required
