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AI accelerator design.pdf

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韩国首尔大学教授讲解的关于设计人工智能（AI）芯片的资料，关于人工智能加速器设计的资料。韩国汉阳大学IDEC课程课件。

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AI Accelerator design & lab

-Hardware IP (SoC) & Memory Design for

Deep Neural Network and Its Application

Date : 2019.04.08

Author : Hyun Kim

Affiliation : Seoul National University of Science and Technology

Electrical and Information Engineering

Position : Assistant Professor

Contact : hyunkim@seoultech.ac.kr / 010-9600-5427

한양대 IDEC 교육

Contents

Self-Introduction

HW IP / SoC Design of Deep Neural Networks Platform in Autonomous Driving

HW IP / SoC Design of Memory for Deep Neural Networks

Conclusion

Introduction

Additional Research Topics related to Memory Design

Contents

Self-Introduction

HW IP / SoC Design of Deep Neural Networks Platform in Autonomous Driving

HW IP / SoC Design of Memory for Deep Neural Networks

Conclusion

Introduction

Additional Research Topics related to Memory Design

About Myself

Self-Introduction

Employment Background

Duration Affiliation Department Title

2018.09~Current

Seoul National University of

Science and Technology

Electrical and Information Engineering Assistant Professor

2016.03~2018.08 Seoul National University BK21+ / Electrical and Computer Engineering BK Professor

2015.03~2016.02 Seoul National University BK21+ / Electrical and Computer Engineering Post Doctor

Education Background

Course Institution Department Duration

Bachelor’s Seoul National University Electrical and Computer Engineering 2005.03~2009.02

Master’s Seoul National University Electrical and Computer Engineering 2009.03~2011.02

Doctorate Seoul National University Electrical and Computer Engineering 2011.03~2015.02

Title of

Dissertation

M.S.

Power-Aware Design with Various Low-Power Algorithms for an

H.264/AVC Encoder

Advisor

M.S. Hyuk-Jae Lee

Ph.D.

H.264-based Low Power Heterogeneous Video Recording System

Ph.D. Hyuk-Jae Lee

Personal Information

Name Date of Birth Nationality

Hyun Kim 1987-02-11 Republic of Korea

Research Experience

Video

Compression

System

Optimization

Digital

System (SoC)

Design

Low-Power

Design

Deep

Learning

 Resource-Performance

Trade-off Design

 R-D Performance vs.

complexity optimization

for Video Codec

 Power Consumption vs.

Accuracy optimization

for Deep Learning

 Memory architecture &

access optimization

 Video Coding Standard

H.264 algorithm & HW design

HEVC algorithm & HW design

 Embedded Compression Design

DWT+SPIHT algorithm & HW design

 Multi-Codec Design

Codec Integration for best performance

 Low-complexity CNN

 GPU/RTL based low-complexity CNN

 CNN for autonomous driving

 Memory for CNN

 Approximate DRAM Architecture

 Next generation memory: HBM/PCRAM

 Processor-In-Memory

HW IP/SoC

Design for

Multimedia

System

Self-Introduction



Multimedia processing

for low-power

 Low-power Video Codec

 Low-power Deep

Learning

 Pre-processing scheme

for low-complexity

Multimedia

HW acceleration

Optimization

 Front-end SoC design

HW acceleration

Post-layout simulation

Front-end (FPGA) verification

HW/SW co-design

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