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Order Number: 280000-003
Intel
®
PXA27x Processor Family
Developer’s Manual
January 2006
ii Intel
®
PXA27x Processor Family Developer’s Manual
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELR PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS
AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS
OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO
FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
PXA27x Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the
license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a
commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this
document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may
be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, the Intel logo, Intel StrataFlash, Intel XScale, and Wireless Intel SpeedStep are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation, 2006. All Rights Reserved.
Intel
®
PXA27x Processor Family Developer’s Manual iii
Contents
Contents:
1 Introduction...................................................................................................................................1-1
1.1 About This Manual.............................................................................................................1-1
1.1.1 Number Representation........................................................................................1-1
1.1.2 Naming Conventions ............................................................................................1-2
1.1.3 Data Types ...........................................................................................................1-2
1.1.4 Related Documents ..............................................................................................1-3
1.2 Product Overview ..............................................................................................................1-4
1.2.1 Intel XScale
®
Technology.....................................................................................1-5
1.2.2 Power Management..............................................................................................1-7
1.2.3 Internal Memory....................................................................................................1-7
1.2.4 Interrupt Controller................................................................................................1-7
1.2.5 Operating-System Timers.....................................................................................1-8
1.2.6 Pulse-Width Modulation Unit (PWM) ....................................................................1-8
1.2.7 Real-Time Clock (RTC).........................................................................................1-9
1.2.8 General-Purpose I/O (GPIO) ................................................................................1-9
1.2.9 Memory Controller ..............................................................................................1-10
1.2.10 DMA Controller ...................................................................................................1-10
1.2.11 Serial Ports .........................................................................................................1-11
1.2.12 LCD Panel Controller..........................................................................................1-14
1.2.13 MultiMediaCard, SD Memory Card, and SDIO Card Controller..........................1-15
1.2.14 Memory Stick Host Controller .............................................................................1-16
1.2.15 Mobile Scalable Link (MSL) Interface .................................................................1-16
1.2.16 Keypad Interface.................................................................................................1-17
1.2.17 Universal Subscriber Identity Module (USIM) Interface......................................1-17
1.2.18 Quick Capture Camera Interface ........................................................................1-18
1.2.19 Test Interface......................................................................................................1-18
1.3 Intel XScale
®
Microarchitecture Compatibility .................................................................1-19
1.3.1 Compatibility Exceptions.....................................................................................1-19
2 System Architecture .....................................................................................................................2-1
2.1 Overview............................................................................................................................2-1
2.2 Intel XScale
®
Technology Implementation Options...........................................................2-1
2.2.1 Interrupt Controller Registers................................................................................2-2
2.2.2 Performance Monitoring Registers .......................................................................2-2
2.2.3 Clock Configuration and Power Management Registers ......................................2-3
2.2.4 Coprocessor Software Debug Registers...............................................................2-3
2.2.5 Coprocessor 15 ....................................................................................................2-3
2.3 Endianness ........................................................................................................................2-6
2.4 I/O Ordering .......................................................................................................................2-7
2.5 Semaphores ......................................................................................................................2-7
2.6 Interrupts............................................................................................................................2-7
2.7 Reset .................................................................................................................................2-8
2.8 Internal Registers.............................................................................................................2-10
2.9 Selecting Peripherals or General-Purpose I/O ................................................................2-10
2.10 Power-On Reset and Boot Operation ..............................................................................2-10
2.11 Power Management.........................................................................................................2-10
iv Intel
®
PXA27x Processor Family Developer’s Manual
Contents
2.12 Signal Descriptions..........................................................................................................2-11
3 Clocks and Power Manager .........................................................................................................3-1
3.1 Overview............................................................................................................................3-1
3.2 Features.............................................................................................................................3-1
3.3 Signal Descriptions............................................................................................................3-2
3.3.1 Hardware Reset (nRESET) ..................................................................................3-3
3.3.2 Internal Reset (nRESET_OUT) ............................................................................3-3
3.3.3 GPIO Wake-Up Sources.......................................................................................3-3
3.3.4 GPIO Reset (nRESET_GPIO/GPIO<1>)..............................................................3-4
3.3.5 Processor Oscillator Input (PXTAL_IN) ................................................................3-4
3.3.6 Processor Oscillator Output (PXTAL_OUT) .........................................................3-4
3.3.7 Processor Clock Input/Output (CLK_PIO/GPIO<9>)............................................3-4
3.3.8 Timekeeping Oscillator Input (TXTAL_IN)............................................................3-4
3.3.9 Timekeeping Oscillator Output (TXTAL_OUT) .....................................................3-4
3.3.10 Timekeeping Clock Output (CLK_TOUT/GPIO<10>)...........................................3-5
3.3.11 Clock Request (CLK_REQ) ..................................................................................3-5
3.3.12 External Clock (CLK_EXT) ...................................................................................3-5
3.3.13 Battery Fault and VDD Fault (nBATT_FAULT, nVDD_FAULT)............................3-5
3.3.14 Power Enable (PWR_EN).....................................................................................3-5
3.3.15 System Power Enable (SYS_EN).........................................................................3-6
3.3.16 Power Manager I
2
C Clock (PWR_SCL/GPIO<3>) ...............................................3-6
3.3.17 Power Manager I
2
C Data (PWR_SDA/GPIO<4>) ................................................3-6
3.3.18 Power Manager Capacitor Pins (PWR_CAP<3:0>)..............................................3-6
3.3.19 Power Manager Supply Output (PWR_OUT) .......................................................3-6
3.3.20 48-MHz Output Clock (48_MHz)...........................................................................3-6
3.4 Reset Manager Operation .................................................................................................3-6
3.4.1 Reset Types..........................................................................................................3-6
3.4.2 Boot Sequences After Reset ................................................................................3-7
3.4.3 Power-On Reset ...................................................................................................3-7
3.4.4 Hardware Reset....................................................................................................3-8
3.4.5 Watchdog Reset ...................................................................................................3-9
3.4.6 GPIO Reset ........................................................................................................3-10
3.4.7 Summary of Module Reset Sensitivity................................................................3-12
3.4.8 Summary of Reset Sequences...........................................................................3-12
3.5 Clocks Manager Operation ..............................................................................................3-13
3.5.1 External Clock Source Selection (CLK_REQ) ....................................................3-16
3.5.2 13-MHz Processor Oscillator ..............................................................................3-17
3.5.3 32.768-kHz Timekeeping Oscillator....................................................................3-18
3.5.4 Peripheral Phase-Locked Loop (312 MHz).........................................................3-19
3.5.5 Core Phase-Locked Loop (Programmable) ........................................................3-19
3.5.6 Functional-Unit Clock Gating ..............................................................................3-21
3.5.7 Modifying Clock Frequencies..............................................................................3-21
3.5.8 Summary of Clock Modes...................................................................................3-33
3.6 Power Manager Operation...............................................................................................3-34
3.6.1 Power Domains ..................................................................................................3-37
3.6.2 Internal Voltage Regulators ................................................................................3-37
3.6.3 Power Manager I
2
C Interface .............................................................................3-39
3.6.4 Power Faults and Imprecise-Data Abort.............................................................3-39
3.6.5 Modifying Power Modes .....................................................................................3-40
Intel
®
PXA27x Processor Family Developer’s Manual v
Contents
3.6.6 Idle Mode ............................................................................................................3-40
3.6.7 Deep-Idle Mode ..................................................................................................3-42
3.6.8 Standby Mode.....................................................................................................3-42
3.6.9 Sleep Mode.........................................................................................................3-45
3.6.10 Deep-Sleep Mode...............................................................................................3-48
3.6.11 Initial Power-On and Deep-Sleep Exit Sequence ...............................................3-51
3.6.12 Summary of Power Modes .................................................................................3-54
3.7 Voltage Manager Operation.............................................................................................3-55
3.7.1 Power Manager I
2
C and Restrictions..................................................................3-55
3.7.2 Voltage-Change Sequencer ...............................................................................3-56
3.7.3 External Voltage Regulator Requirements..........................................................3-59
3.7.4 Sending Commands Using Voltage-Change Sequencer....................................3-59
3.7.5 Behavior During Power-Fault Assertion..............................................................3-63
3.7.6 Using the Voltage Manager ................................................................................3-63
3.8 Register Descriptions.......................................................................................................3-66
3.8.1 Power Manager Registers ..................................................................................3-66
3.8.2 Clocks Manager Registers..................................................................................3-95
3.8.3 Coprocessor 14: Clock and Power Management .............................................3-103
3.9 Register Summary .........................................................................................................3-105
4 Internal Memory............................................................................................................................4-1
4.1 Overview............................................................................................................................4-1
4.2 Features.............................................................................................................................4-1
4.3 Signal Descriptions ............................................................................................................4-1
4.4 Operation ...........................................................................................................................4-1
4.4.1 SRAM Array and Queue .......................................................................................4-2
4.4.2 System Bus Interface............................................................................................4-2
4.4.3 Power Management..............................................................................................4-2
4.5 Register Descriptions.........................................................................................................4-3
4.6 Register Summary .............................................................................................................4-4
5 DMA Controller .............................................................................................................................5-1
5.1 Overview............................................................................................................................5-1
5.2 Features.............................................................................................................................5-1
5.3 Signal Descriptions ............................................................................................................5-2
5.4 Operation ...........................................................................................................................5-2
5.4.1 DMA Channels......................................................................................................5-4
5.4.2 DMA Descriptors...................................................................................................5-6
5.4.3 Transferring Data................................................................................................5-10
5.4.4 Programming Tips ..............................................................................................5-15
5.4.5 Fly-By Transfers .................................................................................................5-17
5.4.6 How DMA Handles Trailing Bytes.......................................................................5-18
5.4.7 Quick Reference to DMA Programming..............................................................5-21
5.4.8 Programming Examples .....................................................................................5-26
5.5 Register Descriptions.......................................................................................................5-31
5.5.1 DMA Request to Channel Map Register (DRCMRx) ..........................................5-31
5.5.2 DMA Descriptor Address Registers (DDADRx) ..................................................5-31
5.5.3 DMA Source Address Register (DSADRx) .........................................................5-33
5.5.4 DMA Target Address Registers (DTADRx).........................................................5-34
5.5.5 DMA Command Registers (DCMDx) ..................................................................5-35
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