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An Introduction to the ARM Cortex-M3 Processor
Shyam Sadasivan October 2006
1. Introduction
System-on-chip solutions based on ARM embedded processors address many different market
segments including enterprise applications, automotive systems, home networking and wireless
technologies. The ARM Cortex™ family of processors provides a standard architecture to address
the broad performance spectrum required by these diverse technologies. The ARM Cortex family
includes processors based on the three distinct profiles of the ARMv7 architecture; the A profile for
sophisticated, high-end applications running open and complex operating systems; the R profile for
real-time systems; and the M profile optimized for cost-sensitive and microcontroller applications.
The Cortex-M3 processor is the first ARM processor based on the ARMv7-M architecture and has
been specifically designed to achieve high system performance in power- and cost-sensitive
embedded applications, such as microcontrollers, automotive body systems, industrial control
systems and wireless networking, while significantly simplifying programmability to make the ARM
architecture an option for even the simplest applications.
1.1 Higher performance through better efficiency
In order to achieve higher performance, processors can either work hard or work smart. Pushing
higher clock frequencies may increase performance but is also accompanied by higher power
consumption and design complexity. On the other hand, higher compute efficiency at slower clock
speeds results in simpler and lower power designs that can perform the same tasks. At the heart of
the Cortex-M3 processor is an advanced 3-stage pipeline core, based on the Harvard architecture,
that incorporates many new powerful features such as branch speculation, single cycle multiply and
hardware divide to deliver an exceptional Dhrystone benchmark performance of 1.25 DMIPS/MHz.
The Cortex-M3 processor also implements the new Thumb
®
-2 instruction set architecture, helping it
to be 70% more efficient per MHz than an ARM7TDMI-S
®
processor executing Thumb instructions,
and 35% more efficient than the ARM7TDMI-S processor executing ARM instructions, for the
Dhrystone benchmark.
1.2 Ease of use for quick and efficient application development
Reducing time-to-market and lowering development costs are critical criteria in the choice of
microcontrollers, and the ability to quickly and easily develop software is key to these requirements.
The Cortex-M3 processor has been designed to be fast and easy to program, with the users not
required to write any assembler code or have deep knowledge of the architecture to create simple
applications. The processor has a simplified stack-based programmer’s model which still maintains
compatibility with the traditional ARM architecture but is analogous to the systems employed by
legacy 8- and 16-bit architectures, making the transition to 32-bit easier. Additionally a hardware-
based interrupt scheme means that writing interrupt service routines (handlers) becomes trivial, and
that start-up code is now significantly simplified as no assembler code register manipulation is
required.
Key new features in the underlying Thumb-2 Instruction Set Architecture (ISA) implement C code
more naturally, with native bitfield manipulation, hardware division and If/Then instructions. Further,
from a development perspective, Thumb-2 instructions speed up development and simplify long
term maintenance and support of compiled objects through automatic optimization for both
performance and code density, without the need for complex interworking between code compiled
for ARM or Thumb modes. The effect of this is that users can maintain their code in C and not have
to create libraries of pre-compiled object code, allowing for far greater code reuse.
2
1.3 Reduced costs and lower power for sensitive markets
A constant barrier to the adoption of higher performance microcontrollers has always been cost.
Advanced manufacturing technologies are expensive and therefore smaller silicon area
requirements can reduce costs significantly. The Cortex-M3 processor reduces system area by
implementing the smallest ARM core to date, with just 33,000 gates in the central core (0.18um G)
and by efficiently incorporating tightly coupled system components in the processor. Memory
requirements are minimized by implementing unaligned data storage, atomic bit manipulation and
the Thumb-2 instruction set that reduces instruction memory requirements for the Dhrystone
benchmark by more than 25% compared to ARM instructions.
In order to address the increasing need for energy conservation in markets like white goods and
wireless networking, the Cortex-M3 processor supports extensive clock gating and integrated sleep
modes. Enabled by these features, the processor delivers a power consumption of just 4.5mW and
a silicon footprint of 0.30mm
2
when implemented at a target frequency of 50MHz on the TSMC
0.13G process using ARM Metro™ standard cells.
1.4 Integrated debug and trace for faster time to market
Embedded systems typically have no graphical user interface making software debug a special
challenge for programmers. In-circuit Emulator (ICE) units have traditionally been used as plug-in
devices to provide a window into the system through a familiar PC interface. As systems get
smaller and more complex, physically attaching such debug units is no longer a viable solution. The
Cortex-M3 processor implements debug technology in the hardware itself with several integrated
components that facilitate quicker debug with trace & profiling, breakpoints, watchpoints and code
patching, significantly reducing time to market. Additionally, the processor provides a high level of
visibility into the system through a traditional JTAG port or the 2-pin Serial Wire Debug (SWD) port
that is suitable for devices in low pin-count packages.
1.5 Migration from the ARM7™ processor family for better performance and
power efficiency
Over the last decade, the ARM7 family of processors has been widely adopted for many
applications. The Cortex-M3 processor builds on this success to present the logical migration path
for ARM7 processor-based systems. The central core offers higher efficiency; a simpler
programming model and excellent deterministic interrupt behaviour, whilst the integrated
peripherals offer enhanced performance at low cost.
Table 1. ARM7TDMI-S and Cortex-M3 comparison (100MHz frequency on TSMC 0.18G)
Features ARM7TDMI-S Cortex-M3
Architecture ARMv4T (von Neumann) ARMv7-M (Harvard)
ISA Support Thumb / ARM Thumb / Thumb-2
Pipeline 3-Stage 3-Stage + branch speculation
Interrupts FIQ / IRQ NMI + 1 to 240 Physical Interrupts
Interrupt Latency 24-42 Cycles 12 Cycles
Sleep Modes None Integrated
Memory Protection None 8 region Memory Protection Unit
Dhrystone 0.95 DMIPS/MHz (ARM mode) 1.25 DMIPS/MHz
Power Consumption 0.28mW/MHz 0.19mW/MHz
Area 0.62mm2 (Core Only) 0.86mm2 (Core & Peripherals)*
* Does not include optional system peripherals (MPU & ETM) or integration level components
3
Figure 1. Relative performance for ARM7TDMI-S (ARM) and Cortex-M3 (Thumb-2)
Figure 2. Relative code size for ARM7TDMI-S (ARM) and Cortex-M3 (Thumb-2)
2. Cortex-M3 processor architecture and features
The Cortex-M3 processor, based on the ARMv7-M architecture, has a hierarchical structure. It
integrates the central processor core, called the CM3Core, with advanced system peripherals to
enable integrated capabilities like interrupt control, memory protection and system debug and trace.
These peripherals are highly configurable to allow the Cortex-M3 processor to address a wide
range of applications and be more closely aligned with the system requirements. The Cortex-M3
core and the integrated components (Figure 3) have been specifically designed to meet the
requirements of minimal memory implementation, reduced pin count and low power consumption.
2.1 The Cortex-M3 Core
The central Cortex-M3 core is based on the Harvard architecture characterized by separate buses
for instructions and data (Figure 3). The processor differs from the von Neumann architecture
based ARM7 family of processors which use the same signal buses and memory for both
instructions and data. By being able to read both an instruction and data from memory at the same
time, the Cortex-M3 processor can perform many operations in parallel, speeding application
execution.
4
Figure 3. The Cortex-M3 processor
The core pipeline has 3 stages: Instruction Fetch,
Instruction Decode and Instruction Execute. When
a branch instruction is encountered, the decode
stage also includes a speculative instruction fetch
that could lead to faster execution. The processor
fetches the branch destination instruction during
the decode stage itself. Later, during the execute
stage, the branch is resolved and it is known
which instruction is to be executed next. If the
branch is not to be taken, the next sequential
instruction is already available. If the branch is to
be taken, the branch instruction is made available
at the same time as the decision is made,
restricting idle time to just one cycle.
The Cortex-M3 core contains a decoder for
traditional Thumb and new Thumb-2 instructions,
an advanced ALU with support for hardware
multiply and divide, control logic, and interfaces to
the other components of the processor.
The Cortex-M3 processor is a 32-bit processor,
with a 32-bit wide data path, register bank and
memory interface. There are 13 general-purpose
registers, two stack pointers, a link register, a
program counter and a number of special
registers including a program status register.
The Cortex-M3 processor supports two operating
modes, Thread and Handler and two levels of
access for the code, privileged and unprivileged,
enabling the implementation of complex and open
systems without sacrificing the security of the
application. Unprivileged code execution limits or excludes access to some resources like certain
instructions and specific memory locations. The Thread mode is the typical operating mode and
supports both privileged and unprivileged code. The Handler mode is entered when an exception
occurs and all code is privileged during this mode. In addition, all operation is categorized under
two operating states, Thumb for normal execution and Debug for debug activities.
The Cortex-M3 processor is a memory mapped system with a simple, fixed memory map for up to 4
gigabytes of addressable memory space with predefined, dedicated addresses for code
(code space), SRAM(memory space), external memories/devices and internal/external peripherals.
There is also a special region to provide for vendor specific addressability.
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