TMS320DM642参考手册资源-CSDN文库

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TheTMS320C64xDSPs(including the TMS320DM642device)arethe highest-performancefixed-point DSPgenerationin the TMS320C6000™DSPplatform.TheTMS320DM642(DM642) deviceis basedon the second-generation high-performance, advanced VelociTI™very-long-instruction-word (VLIW) architecture(VelociTI.2™) developedbyTexasInstruments (TI), makingthese DSPsanexcellentchoice for digitalmediaapplications.TheC64x™is acode-compatiblememberofthe C6000™DSPplatform. ### TMS320DM642参考手册关键知识点解析 #### 一、TMS320DM642概述 - **定义与背景**：TMS320DM642是德州仪器（Texas Instruments, TI）出品的一款高性能固定点数字信号处理器（Digital Signal Processor, DSP），属于TMS320C6000™系列平台中的第二代产品。它基于VelociTI.2™架构，特别适合于数字媒体应用。 #### 二、架构与性能特点 - **核心架构**：采用第二代高性能量产非常长指令字(Very Long Instruction Word, VLIW)架构——VelociTI.2™。 - **指令周期时间**：支持2纳秒(ns)、1.67纳秒(ns)、1.39纳秒(ns)三种不同周期时间，分别对应500MHz、600MHz、720MHz的工作频率。 - **指令吞吐量**：每个时钟周期可执行八个32位指令。 - **最大性能**：在最高工作频率下，达到5760MIPS（Million Instructions Per Second）。 - **兼容性**：与C64x™系列DSP完全软件兼容。 #### 三、内存管理与外部接口 - **外部内存空间**：支持高达1024兆字节(Byte)的外部内存地址空间。 - **增强型直接内存访问(EDMA)**：集成有64个独立通道的EDMA控制器，用于高效的数据传输。 - **10/100Mbps以太网介质接入控制(EMAC)**：符合IEEE 802.3标准，支持多种网络通信协议。 - **多路视频端口**：包含三个可配置的视频端口，能够无粘合地连接到常见的视频解码器和编码器设备。 - **主机端口接口(HPI)**：提供32/16位的HPI接口，用于与主机进行数据交换。 #### 四、内部组件与功能单元 - **高度独立的功能单元**：集成了八个高度独立的功能单元，包括六个算术逻辑单元(ALU)和支持四个16×16位乘法运算的两个乘法器。 - **算术逻辑单元(ALU)**：每个ALU支持单个32位、双16位或四8位算术操作。 - **多通道音频串行端口(McASP)**：支持八路串行数据输入输出，适用于各种数字音频格式。 #### 五、其他特性与接口 - **管理数据输入输出(MDIO)**：用于管理和控制网络设备。 - **视频时钟控制插值接口(VIC)**：提供时钟控制功能，支持视频和音频同步。 - **外围部件互连(PCI)接口**：符合PCI规范2.2版本，支持32位/66MHz的PCI总线，提供主/从接口模式。 - **集成电路总线(I2C Bus)接口**：实现设备间简单的双向通信。 #### 六、指令集与编程特性 - **指令集扩展**：支持VelociTI.2™扩展，增强了对复杂算法的支持。 - **条件执行**：所有指令均支持条件执行，提高了代码效率。 - **数据类型**：支持8位、16位、32位和64位数据类型。 - **特殊指令**：提供了比特域提取、设置、清除等高级指令。 #### 七、内存管理与数据处理 - **非对齐存储支持**：支持非对齐的内存访问，简化了编程复杂度。 - **通用寄存器**：拥有64个32位通用寄存器，用于存储中间计算结果和其他数据。 - **指令打包**：通过指令打包技术减少代码大小，提高程序执行效率。 #### 八、总结 TMS320DM642是一款专为数字媒体处理设计的高度优化DSP处理器。其独特的VelociTI.2™架构、强大的算术处理能力以及丰富的外设接口使其成为视频处理、图像分析、音频编解码等多种应用场景的理想选择。此外，该处理器还具备高度的软件兼容性和易于编程的特点，进一步提升了其在实际项目中的应用价值。

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TMS320DM642

www.ti.com

SPRS200N–JULY 2002–REVISED OCTOBER 2010

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

Check for Samples: TMS320DM642

1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor

123

– 1024M-Byte Total Addressable External

• High-Performance Digital Media Processor

Memory Space

– 2-, 1.67-, 1.39-ns Instruction Cycle Time

• Enhanced Direct-Memory-Access (EDMA)

– 500-, 600-, 720-MHz Clock Rate

Controller (64 Independent Channels)

– Eight 32-Bit Instructions/Cycle

• 10/100 Mb/s Ethernet MAC (EMAC)

– 4000, 4800, 5760 MIPS

– IEEE 802.3 Compliant

– Fully Software-Compatible With C64x™

– Media Independent Interface (MII)

• VelociTI.2™ Extensions to VelociTI™

– 8 Independent Transmit (TX) Channels and 1

Advanced Very-Long-Instruction-Word (VLIW)

Receive (RX) Channel

TMS320C64x™ DSP Core

• Management Data Input/Output (MDIO)

– Eight Highly Independent Functional Units

• Three Configurable Video Ports

With VelociTI.2™ Extensions:

– Providing a Glueless I/F to Common Video

• Six ALUs (32-/40-Bit), Each Supports

Decoder and Encoder Devices

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

Arithmetic per Clock Cycle – Supports Multiple Resolutions/Video Stds

• Two Multipliers Support Four 16 x 16-Bit • VCXO Interpolated Control Port (VIC)

Multiplies (32-Bit Results) per Clock

– Supports Audio/Video Synchronization

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

• Host-Port Interface (HPI) [32-/16-Bit]

Results) per Clock Cycle

• 32-Bit/66-MHz, 3.3-V Peripheral Component

– Load-Store Architecture With Non-Aligned

Interconnect (PCI) Master/Slave Interface

Support

Conforms to PCI Specification 2.2

– 64 32-Bit General-Purpose Registers

• Multichannel Audio Serial Port (McASP)

– Instruction Packing Reduces Code Size

– Eight Serial Data Pins

– All Instructions Conditional

– Wide Variety of I

S and Similar Bit Stream

• Instruction Set Features

Formats

– Byte-Addressable (8-/16-/32-/64-Bit Data)

– Integrated Digital Audio I/F Transmitter

– 8-Bit Overflow Protection Supports S/PDIF, IEC60958-1, AES-3, CP-430

Formats

– Bit-Field Extract, Set, Clear

• Inter-Integrated Circuit ( I

C Bus™)

– Normalization, Saturation, Bit-Counting

• Two Multichannel Buffered Serial Ports

– VelociTI.2™ Increased Orthogonality

• Three 32-Bit General-Purpose Timers

• L1/L2 Memory Architecture

• Sixteen General-Purpose I/O (GPIO) Pins

– 128K-Bit (16K-Byte) L1P Program Cache

(Direct Mapped) • Flexible PLL Clock Generator

– 128K-Bit (16K-Byte) L1D Data Cache (2-Way • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible

Set-Associative)

• 548-Pin Ball Grid Array (BGA) Package

– 2M-Bit (256K-Byte) L2 Unified Mapped (GDK and ZDK Suffixes), 0.8-mm Ball Pitch

RAM/Cache (Flexible RAM/Cache Allocation)

• 548-Pin Ball Grid Array (BGA) Package

• Endianess: Little Endian, Big Endian (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch

• 64-Bit External Memory Interface (EMIF) • 0.13-µm/6-Level Cu Metal Process (CMOS)

– Glueless Interface to Asynchronous • 3.3-V I/O, 1.2-V Internal (-500)

Memories (SRAM and EPROM) and

• 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600,

Synchronous Memories (SDRAM, SBSRAM,

-720)

ZBT SRAM, and FIFO)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Windows is a registered trademark of Microsoft Corporation.

C Bus is a trademark of Philips Electronics N.V..

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS320DM642

SPRS200N–JULY 2002–REVISED OCTOBER 2010

www.ti.com

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point

DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on

the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)

architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice

for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the

DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The

DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of

array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length

and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic

units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units

include new instructions to accelerate the performance in video and imaging applications and extend the

parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates

(MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for

a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory,

and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.

The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is

a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory

space that is shared between program and data space. L2 memory can be configured as mapped

memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a

10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO

interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated

circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose

timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component

interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event

generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of

interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port

peripherals provide a glueless interface to common video decoder and encoder devices. The DM642

video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,

BT.1120, SMPTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video

display modes. Each video port consists of two channels — A and B with a 5120-byte capture/display

buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated

Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can

be individually allocated to any of the two zones. The serial port supports time-division multiplexing on

each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins

transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on

multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC

Sound (I

S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,

CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of

user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection

circuit for each high-frequency master clock which verifies that the master clock is within a programmed

frequency range.

Submit Documentation Feedback

Product Folder Link(s): TMS320DM642

TMS320DM642

www.ti.com

SPRS200N–JULY 2002–REVISED OCTOBER 2010

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits

to up to 16-bits. The output of the VIC is a single bit interpolated D/A output.For more details on the VIC

port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide

(literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP

core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10

Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of

service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows

efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP

Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference

Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to

enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the

MDIO module transparently monitors its link state by reading the PHY status register. Link change events

are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link

status of the device without continuously performing costly MDIO accesses. For more details on the

MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data

Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices and

communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP)

can be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM642 has a complete set of development tools which includes: a new C compiler, an assembly

optimizer to simplify programming and scheduling, and a Windows

debugger interface for visibility into

source code execution.

1.1 Device Compatibility

The DM642 device is a code-compatible member of the C6000™ DSP platform.

The C64x™ DSP generation of devices has a diverse and powerful set of peripherals.

For more detailed information on the device compatibility and similarities/differences among the DM642

and other C64x™ devices, see the TMS320DM642 Technical Overview (literature number SPRU615).

Submit Documentation Feedback

Product Folder Link(s): TMS320DM642

TMS320DM642

www.ti.com

SPRS200N–JULY 2002–REVISED OCTOBER 2010

1 TMS320DM642 Video/Imaging Fixed-Point Digital 5 DM642 Peripheral Information and Electrical

Signal Processor ........................................ 1 Specifications .......................................... 71

5.1 Parameter Information .............................. 71

1.1 Device Compatibility ................................. 3

5.2 Recommended Clock and Control Signal Transition

1.2 Functional Block Diagram ............................ 4

Behavior ............................................ 72

2 Device Overview ........................................ 6

5.3 Power Supplies ..................................... 73

2.1 Device Characteristics ............................... 6

5.4 Enhanced Direct Memory Access (EDMA)

2.2 CPU (DSP Core) Description ........................ 7

Controller ........................................... 77

2.3 Memory Map Summary ............................. 13

5.5 Interrupts ............................................ 81

5.6 Reset ............................................... 83

2.4 Bootmode ........................................... 16

5.7 Clock PLL ........................................... 86

2.5 Pin Assignments .................................... 16

5.8 External Memory Interface (EMIF) ................. 92

2.6 Development ........................................ 50

5.9 Multichannel Audio Serial Port (McASP0) Peripheral

3 Device Configurations ................................ 54

..................................................... 108

3.1 Configurations at Reset ............................ 54

5.10 Inter-Integrated Circuit (I2C) ...................... 116

3.2 Configurations After Reset ......................... 56

5.11 Host-Port Interface (HPI) .......................... 122

3.3 Peripheral Configuration Lock ...................... 59

5.12 Peripheral Component Interconnect (PCI) ........ 128

3.4 Device Status Register Description ................ 61

5.13 Multichannel Buffered Serial Port (McBSP) ....... 132

3.5 Multiplexed Pin Configurations ..................... 63

5.14 Video Port ......................................... 141

3.6 Debugging Considerations ......................... 65

5.15 VCXO Interpolated Control (VIC) ................. 149

5.16 Ethernet Media Access Controller (EMAC) ....... 151

3.7 Configuration Examples ............................ 65

5.17 Management Data Input/Output (MDIO) .......... 157

4 Device Operating Conditions ....................... 69

5.18 Timer .............................................. 159

4.1 Absolute Maximum Ratings Over Operating Case

Temperature Range

5.19 General-Purpose Input/Output (GPIO) ............ 161

(Unless Otherwise Noted) ................................. 69

5.20 JTAG .............................................. 164

4.2 Recommended Operating Conditions .............. 69

Revision History ........................................... 166

4.3 Electrical Characteristics Over Recommended

6 Mechanical Data ...................................... 167

Ranges of Supply Voltage and Operating Case

6.1 Thermal Data ...................................... 167

Temperature (Unless Otherwise Noted) ............ 70

6.2 Packaging Information ............................ 169

Submit Documentation Feedback

Product Folder Link(s): TMS320DM642

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