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AD9851

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400 MSPS 14-Bit, 1.8 V CMOS

Direct Digital Synthesizer

AD9951

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

FEATURES

400 MSPS internal clock speed

Integrated 14-bit DAC

32-bit tuning word

Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)

Excellent dynamic performance

>80 dB SFDR @ 160 MHz (±100 kHz offset) A

OUT

Serial I/O control

1.8 V power supply

Software and hardware controlled power-down

48-lead TQFP/EP package

Support for 5 V input levels on most digital inputs

PLL REFCLK multiplier (4× to 20×)

Internal oscillator, can be driven by a single crystal

Phase modulation capability

Multichip synchronization

APPLICATIONS

Agile LO frequency synthesis

Programmable clock generators

Test and measurement equipment

Acousto-optic device drivers

FUNCTIONAL BLOCK DIAGRAM

COS(X)

CONTROL REGISTERS

OSCILLATOR/BUFFER

SYNC

ENABLE

I/O UPDATE

DAC_R

SET

DDS CORE

PHASE

OFFSET

PHASE

ACCUMULATOR

–1

IOUT

OSK

PWRDWNCTL

REFCLK

CRYSTAL OUT I/O PORTPS<1:0>

DDS CLOCK

FREQUENCY

TUNING WORD

CLEAR PHASE

ACCUMULATOR

AMPLITUDE

SCALE FACTOR

DAC

SYSTEM

CLOCK

SYSTEM

CLOCK

SYNC_IN

SYNC_CLK

RESET

TIMING AND CONTROL LOGIC

4×–20×

CLOCK

MULTIPLIER

÷ 4

AD9951

19 14

03359-0-001

Figure 1.

AD9951

Rev. 0 | Page 2 of 28

TABLE OF CONTENTS

General Description ......................................................................... 3

AD9951—Electrical Specifications ................................................ 4

Absolute Maximum Ratings............................................................ 6

Pin Configuration............................................................................. 7

Pin Function Descriptions .............................................................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Component Blocks..................................................................... 12

Modes of Operation ................................................................... 17

Programming AD9951 Features............................................... 17

Serial Port Operation................................................................. 20

Instruction Byte.......................................................................... 22

Serial Interface Port Pin Description....................................... 22

MSB/LSB Transfers .................................................................... 22

Suggested Application Circuits..................................................... 24

Outline Dimensions....................................................................... 25

ESD Caution................................................................................ 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

Revision 0: Initial Version

AD9951

Rev. 0 | Page 3 of 28

GENERAL DESCRIPTION

The AD9951 is a direct digital synthesizer (DDS) featuring a

14-bit DAC operating up to 400 MSPS. The AD9951 uses

advanced DDS technology, coupled with an internal high speed,

high performance DAC to form a digitally programmable,

complete high frequency synthesizer capable of generating a

frequency-agile analog output sinusoidal waveform at up to

200 MHz. The AD9951 is designed to provide fast frequency

hopping and fine tuning resolution (32-bit frequency tuning

word). The frequency tuning and control words are loaded into

the AD9951 via a serial I/O port.

The AD9951 is specified to operate over the extended industrial

temperature range of –40°C to +105°C.

AD9951

Rev. 0 | Page 4 of 28

AD9951—ELECTRICAL SPECIFICATIONS

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R

SET

= 3.92 kΩ, External Reference Clock

Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.

Parameter Temp Min Typ Max Unit

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled FULL 1 400 MHz

REFCLK Multiplier Enabled at 4× FULL 20 100 MHz

REFCLK Multiplier Enabled at 20× FULL 4 20 MHz

Input Capacitance 25°C 3 pF

Input Impedance 25°C 1.5 kΩ

Duty Cycle 25°C 50 %

Duty Cycle with REFCLK Multiplier Enabled 25°C 35 65 %

REFCLK Input Power

FULL –15 0 +3 dBm

DAC OUTPUT CHARACTERISTICS

Resolution 14 Bits

Full-Scale Output Current 25°C 5 10 15 mA

Gain Error 25°C –10 +10 %FS

Output Offset 25°C 0.6 µA

Differential Nonlinearity 25°C 1 LSB

Integral Nonlinearity 25°C 2 LSB

Output Capacitance 25°C 5 pF

Residual Phase Noise @ 1 kHz Offset, 40 MHz A

OUT

REFCLK Multiplier Enabled @ 20× 25°C –105 dBc/Hz

REFCLK Multiplier Enabled @ 4× 25°C –115 dBc/Hz

REFCLK Multiplier Disabled 25°C –132 dBc/Hz

Voltage Compliance Range 25°C AVDD – 0.5 AVDD + 0.5 V

Wideband SFDR

1 MHz to 10 MHz Analog Out 25°C 73 dBc

10 MHz to 40 MHz Analog Out 25°C 67 dBc

40 MHz to 80 MHz Analog Out 25°C 62 dBc

80 MHz to 120 MHz Analog Out 25°C 58 dBc

120 MHz to 160 MHz Analog Out 25°C 52 dBc

Narrow-Band SFDR

40 MHz Analog Out (±1 MHz) 25°C 87 dBc

40 MHz Analog Out (±250 kHz) 25°C 89 dBc

40 MHz Analog Out (±50 kHz) 25°C 91 dBc

40 MHz Analog Out (±10 kHz) 25°C 93 dBc

80 MHz Analog Out (±1 MHz) 25°C 85 dBc

80 MHz Analog Out (±250 kHz) 25°C 87 dBc

80 MHz Analog Out (±50 kHz) 25°C 89 dBc

80 MHz Analog Out (±10 kHz) 25°C 91 dBc

120 MHz Analog Out (±1 MHz) 25°C 83 dBc

120 MHz Analog Out (±250 kHz) 25°C 85 dBc

120 MHz Analog Out (±50 kHz) 25°C 87 dBc

120 MHz Analog Out (±10 kHz) 25°C 89 dBc

160 MHz Analog Out (±1 MHz) 25°C 81 dBc

160 MHz Analog Out (±250 kHz) 25°C 83 dBc

160 MHz Analog Out (±50 kHz) 25°C 85 dBc

160 MHz Analog Out (±10 kHz) 25°C 87 dBc

AD9951

Rev. 0 | Page 5 of 28

Parameter Temp Min Typ Max Unit

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency FULL 25 Mbps

Minimum Clock Pulse Width Low FULL 7 ns

Minimum Clock Pulse Width High FULL 7 ns

Maximum Clock Rise/Fall Time FULL 2 ns

Minimum Data Setup Time DVDD_I/O = 3.3 V FULL 3 ns

Minimum Data Setup Time DVDD_I/O = 1.8 V FULL 5 ns

Minimum Data Hold Time FULL 0 ns

Maximum Data Valid Time FULL 25 ns

Wake-Up Time

FULL 1 ms

Minimum Reset Pulse Width High FULL 5 SYSCLK Cycles

I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 4 ns

I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 6 ns

I/O UPDATE, SYNC_CLK Hold Time FULL 0 ns

Latency

I/O UPDATE to Frequency Change Prop Delay 25°C 24 SYSCLK Cycles

I/O UPDATE to Phase Offset Change Prop Delay 25°C 24 SYSCLK Cycles

I/O UPDATE to Amplitude Change Prop Delay 25°C 16 SYSCLK Cycles

CMOS LOGIC INPUTS

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 1.25 V

Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 0.6 V

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 2.2 V

Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 0.8 V

Logic 1 Current 25°C 3 12 µA

Logic 0 Current 25°C 12 µA

Input Capacitance 25°C 2 pF

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V

Logic 1 Voltage 25°C 1.35 V

Logic 0 Voltage 25°C 0.4 V

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V

Logic 1 Voltage 25°C 2.8 V

Logic 0 Voltage 25°C 0.4 V

POWER CONSUMPTION (AVDD = DVDD = 1.8 V)

Single-Tone Mode 25°C 162 171 mW

Rapid Power-Down Mode 25°C 150 160 mW

Full-Sleep Mode 25°C 20 27 mW

SYNCHRONIZATION FUNCTION

Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V) 25°C 62.5 MHz

Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V) 25°C 100 MHz

SYNC_CLK Alignment Resolution

25°C ±1 SYSCLK Cycles

To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-

formance of the device.

Wake-up time refers to the recovery from analog power-down modes (see the section). The longest time required is for the

reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values

are used.

Power-Down Functions of the AD9951

SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-

quency is the same as the external reference clock frequency.

SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.

This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock

edges are aligned, the synchronization function should not increase the skew between the two edges.

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