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QuadSPI
Microcontrollers Division
Application Team
Introduction
02/07/
2015
19
QUADSPI
Overview
• Communication interface for single/dual/quad SPI flash memories
• Three operating modes
– Indirect : all the operations are performed through registers (classical SPI)
– Status polling : periodical read of the flash status registers (interrrupt
generation)
– Memory mapped : External flash seen as internal for read operations
20
Registers /
Control
Clock
Management
Shift RegisterFIFO
QSPI Flash
CLK
BK1_IO0/SO
BK1_IO1/SI
BK1_IO2
BK1_IO3
BK1_nCS
AHB
CLK
Q0/SI
Q1/SO
Q2/nWP
Q3/nHOLD
nCS
Dual-quad mode
• Access two flashes in parrallel with the same frame format
and the same instruction (8-bit par cycle)
21
QUADSPI
Registers /
Control
Clock
Management
Shift Register
FIFO
QSPI Flash
CLK
BK1_IO0/SO
BK1_IO1/SI
BK1_IO2
BK1_IO3
BK1_nCS
AHB
CLK
Q0/SI
Q1/SO
Q2/nWP
Q3/nHOLD
nCS
QSPI Flash
BK2_IO0/SO
BK2_IO1/SI
BK2_IO2
BK2_IO3
BK2_nCS
CLK
Q0/SI
Q1/SO
Q2/nWP
Q3/nHOLD
nCS
Main features
• Three functional modes:
– Indirect
– Status-polling
– Memory-mapped
• Optimized operations
– SDR and DDR support
• Fully programmable
– Opcode for both indirect and memory mapped mode
– Frame format for both indirect and memory mapped
mode
• Integrated FIFO for reception and transmission
– 8, 16, and 32-bit data accesses are allowed
– DMA channel for indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error
22
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