ucos在ARM上的移植,lcd驱动,触摸屏校准S3C2440

#define MVAL (13) // #define MVAL_USED (0) //0=each frame 1=rate by MVAL #define INVVDEN (1) //0=normal 1=inverted #define BSWP (0) //Byte swap control #define HWSWP (1) //Half word swap control #define M5D(n) ((n) & 0x1fffff) // To get lower 21bits #define VBPD (5) //垂直同步信号的后肩 #define VFPD (14) //垂直同步信号的前肩 #define VSPW (1) //垂直同步信号的脉宽 #define HBPD (35) //水平同步信号的后肩 #define HFPD (19) //水平同步信号的前肩 #define HSPW (5) //水平同步信号的脉宽 #define CLKVAL_TFT (4) //FCLK=180MHz,HCLK=90MHz,VCLK=6.5MHz // GPB1/TOUT1 for Backlight control(PWM) #define GPB1_TO_OUT() (rGPBUP &= 0xfffd, rGPBCON &= 0xfffffff3, rGPBCON |= 0x00000004) #define GPB1_TO_1() (rGPBDAT |= 0x0002) #define GPB1_TO_0() (rGPBDAT &= 0xfffd) static void Lcd_Init(void) { rGPCUP = 0x00000000; //0: The pull up function is enabled rGPCCON = 0xaaaa02a9; //1010,0000,0010,1010,1001 //GPC1 10 = VCLK GPC0 01 = Output //GPC3 10 = VFRAME GPC2 10 = VLINE //GPC4 10 = VM //GPC9 10 = VD[1] GPC8 10 = VD[0] // rGPDUP=0xffffffff; // Disable Pull-up register rGPDUP = 0x00000000; rGPDCON=0xaaaaaaaa; //Initialize VD[15:8] rLCDCON1=(CLKVAL_TFT<<8)|(MVAL_USED<<7)|(3<<5)|(12<<1)|0; // TFT LCD panel,16bpp TFT,ENVID=off //1100 = 16 bpp for TFT //(12<<1) //(3<<5) TFT LCD //MMODE [7] Determine the toggle rate of the VM. //0 = Each Frame 1 = The rate defined by the MVAL //#define CLKVAL_TFT (4) //(CLKVAL_TFT<<8) //TFT: VCLK = HCLK / [(CLKVAL+1) x 2] 10M //#elif FCLK==400000000 //#define HCLK (FCLK/4) 100M //#define PCLK (HCLK/2) rLCDCON2= (VBPD<<24)|(LINEVAL_TFT<<14)|(VFPD<<6)|(VSPW); rLCDCON3=(HBPD<<19)|(HOZVAL_TFT<<8)|(HFPD); rLCDCON4=(MVAL<<8)|(HSPW); rLCDCON5 = (1<<11) | (1<<10) | (1<<9) | (1<<8) | (0<<7) | (0<<6) | (1<<3) |(BSWP<<1) | (HWSWP); //5:6:5 VCLK rising edge (1 = Enable PWREN signal) BSWP=0,HWSWP=1; //VSYNC(Frame Rate) = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) //+ (HBPD+1) //+ (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ] {(1+1)+(5+1)+(240)+(14+1)} x {(5+1)+(35+1)+(19+1)+(320)} x {2 x (4+1)/ (100M)} =263 x 382 x 1/10M //VSYNC =99 rLCDSADDR1=(((U32)LCD_BUFFER>>22)<<21)|M5D((U32)LCD_BUFFER>>1); rLCDSADDR2=M5D( ((U32)LCD_BUFFER+(SCR_XSIZE_TFT*LCD_TFT_YSIZE*2))>>1 ); rLCDSADDR3=(((SCR_XSIZE_TFT-LCD_TFT_XSIZE)/1)<<11)|(LCD_TFT_XSIZE/1); rLCDINTMSK|=(3); // MASK LCD Sub Interrupt rTCONSEL &= (~7) ; // Disable LPC3480 rTPAL=0; // Disable Temp Palette } GPG4 [9:8] 00 = Input 01 = Output 10 = EINT[12] 11 = LCD_PWRDN rLCDCON1|=1; // ENVID=ON