Publication Release Date: May, 2006
-III- Revision 0.42
W83627DHG
7.2.1 UART Control Register (UCR) (Read/Write) ..................................................................40
7.2.2 UART Status Register (USR) (Read/Write) ....................................................................43
7.2.3 Handshake Control Register (HCR) (Read/Write) ..........................................................43
7.2.4 Handshake Status Register (HSR) (Read/Write)............................................................44
7.2.5 UART FIFO Control Register (UFR) (Write only)............................................................45
7.2.6 Interrupt Status Register (ISR) (Read only)....................................................................45
7.2.7 Interrupt Control Register (ICR) (Read/Write) ................................................................46
7.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)...............................................46
7.2.9 User-defined Register (UDR) (Read/Write) ....................................................................47
8. PARALLEL PORT ..................................................................................................................... 48
8.1 Printer Interface Logic................................................................................................... 48
8.2 Enhanced Parallel Port (EPP) ...................................................................................... 49
8.2.1 Data Port (Data Swapper) ..............................................................................................49
8.2.2 Printer Status Buffer .......................................................................................................49
8.2.3 Printer Control Latch and Printer Control Swapper ........................................................50
8.2.4 EPP Address Port...........................................................................................................51
8.2.5 EPP Data Port 0-3..........................................................................................................51
8.2.6 EPP Pin Descriptions .....................................................................................................51
8.2.7 EPP Operation ...............................................................................................................52
8.3 Extended Capabilities Parallel (ECP) Port ................................................................... 52
8.3.1 ECP Register and Bit Map..............................................................................................53
8.3.2 Data and ecpAFifo Port ..................................................................................................54
8.3.3 Device Status Register (DSR) ........................................................................................54
8.3.4 Device Control Register (DCR) ......................................................................................55
8.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010 ................................................................55
8.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011.....................................................................55
8.3.7 TFIFO (Test FIFO Mode) Mode = 110............................................................................56
8.3.8 CNFGA (Configuration Register A) Mode = 111.............................................................56
8.3.9 CNFGB (Configuration Register B) Mode = 111.............................................................56
8.3.10 ECR (Extended Control Register) Mode = all ...............................................................57
8.3.11 ECP Pin Descriptions ...................................................................................................58
8.3.12 ECP Operation .............................................................................................................59
8.3.13 FIFO Operation.............................................................................................................59
8.3.14 DMA Transfers .............................................................................................................59
8.3.15 Programmed I/O (NON-DMA) Mode.............................................................................60
8.4 Extension FDD Mode (EXTFDD).................................................................................. 60
8.5 Extension 2FDD Mode (EXT2FDD).............................................................................. 60
9. KEYBOARD CONTROLLER..................................................................................................... 61
9.1 Output Buffer................................................................................................................. 61
9.2 Input Buffer ................................................................................................................... 61
9.3 Status Register ............................................................................................................. 62
9.4 Commands.................................................................................................................... 62
9.5 Hardware GATEA20/Keyboard Reset Control Logic.................................................... 63
9.5.1 KB Control Register (Logic Device 5, CR-F0) ................................................................64
9.5.2 Port 92 Control Register (Default Value = 0x24) ............................................................64
9.6 OnNow / Security Keyboard and Mouse Wake-Up ...................................................... 65
9.6.1 Keyboard Wake-Up Function .........................................................................................65
9.6.2 Keyboard Password Wake-Up Function.........................................................................65
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2010-03-08
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上海伯环自动化2012-09-13谢谢，帮了大忙。重刷了BIOS，很好
