Introduction
The need for Signal Integrity (SI) analysis for printed circuit board (PCB) design has become essential to ensure
first time success of high-speed, high-density digital designs. This paper will cover the usage of Cadence’s
Allegro PCB SI tool for the design of a dual data rate (DDR) memory interface in one of Motorola’s products.
Specifically, this paper will describe the following key phases of the high-speed design process:
• Design set-up
• Pre-route SI analysis
• Constraint-driven routing
• Post-route SI analysis
DDR interfaces, being source synchronous in nature, feature skew as the fundamental parameter to manage in
order to meet setup and hold timing margins. A brief overview of source synchronous signaling and its
challenges is also presented to provide context.
Project Background
This paper is based on the design of a DDR interface in an iDEN Subscriber Group phone that uses the mobile
Linux Java platform. The phone is currently in the final stages of system and factory testing, and is due to be
released in the market at the end of August 2007 for Nextel international customers. The phone has a dual-core
custom processor with an application processor (ARM 11) and a baseband processor (StarCore) running at
400MHz and 208MHz respectively. The processor has a NAND and DDR controller, both supporting 16-bit
interfaces. The memory device used is a multi-chip package (MCP) with stacked NAND (512Mb) and DDR
(512Mb) parts. The NAND device is run at 22MHz and the DDR at 133MHz. The interface had to be
supported over several memory vendors, and consequently had to account for the difference in timing margins,
input capacitances, and buffer drive strengths between different dies and packages.
As customer preference for smaller and thinner phones grows, the design and placement of critical components
and modules has become more challenging. In addition to incorporating various sections such as Radio
Frequency (RF), Power Management, DC, Audio, Digital ICs, and sub-circuits of these modules, design
engineers must simultaneously satisfy the rigid placement requirements for components such as speakers,
antennas, displays, and cameras. As such, there are very few options and little flexibility in terms of placement
of the components. This problem was further accentuated by the fact that several layers of the 10 layer board
(3-4-3 structure with one ground plane and no power planes) were reserved for power, audio, and other high
frequency (RF) nets, leaving engineers with few layers to choose from for digital circuitry.
