Output: Gerber Files
Type : Gerber
From : Variant [[No Variations]] of Project [minisys.PrjPCB]
Generated File[minisys20190712.RUL]
Generated File[minisys20190712.EXTREP]
Generated File[minisys20190712.REP]
Files Generated : 3
Documents Printed : 0
Finished Output Generation At 15:00:19 On 2019/7/12
STM32F103ZET6最小系统板的AD文件
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2024-02-29
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STM32F103ZET6最小系统板.zip （64个子文件） 
STM32F103ZET6最小系统板 
minisys_S4-202009.PcbDoc 8.08MB OV7725.SchDoc 24KB Project Outputs for minisys 
Design Rule Check - minisys20190712.html 9KB minisys20190712.EXTREP 602B minisys20190712-macro.APR_LIB 0B minisys20190712.RUL 425B Design Rule Check - minisys.drc 41KB Design Rule Check - minisys20190712.drc 966B minisys20190712.REP 116B Design Rule Check - MY-PRMPHO-100_20180622.drc 71KB Design Rule Check - minisys.html 434KB
Status Report.Txt 329B Design Rule Check - minisys20190711.html 422KB minisys20190712.apr 0B Design Rule Check - MY-PRMPHO-100_20180622.html 1.04MB Design Rule Check - minisys20190711.drc 38KB
minisys20190712.xlsx 11KB Project Outputs for minisys_S2 Design Rule Check - minisys_S2-20190719.drc 1003B Design Rule Check - minisys_S2-20190719.html 10KB KEY.SchDoc 21KB STEP_MOTOR.SchDoc 17KB Project Logs for minisys_S2 minisys_S2-20190719 PCB ECO 2020-9-11 16-25-57.LOG 922B minisys_S2-20190719 PCB ECO 2020-9-11 17-28-26.LOG 4KB minisys_S2-20190719 PCB ECO 2020-9-11 16-28-46.LOG 842B minisys_S2-20190719 PCB ECO 2020-9-11 17-09-22.LOG 981B minisys_S2-20190719 PCB ECO 2020-9-11 16-32-00.LOG 442B minisys_S2-20190719 PCB ECO 2020-9-11 16-53-51.LOG 6KB minisys_S2-20190719 PCB ECO 2020-9-11 16-20-04.LOG 12KB minisys_S2-20190719 PCB ECO 2020-9-11 17-36-07.LOG 1KB minisys_S2-20190719 PCB ECO 2020-9-11 17-14-04.LOG 1KB ADC_INPUT.SchDoc 38KB DAC.SchDoc 49KB
minisys_S4-202009.rar 5.86MB KEYBOARD.SchDoc 14KB History 
DAC.~(2).SchDoc.Zip 6KB mcu.~(1).SchDoc.Zip 26KB mcu.~(2).SchDoc.Zip 26KB minisys_S2-20190719.~(2).PcbDoc.Zip 5.43MB POWER.~(1).SchDoc.Zip 20KB ADC_INPUT.~(1).SchDoc.Zip 6KB minisys_S2.~(1).PrjPCB.Zip 5KB minisys_S2.~(2).PrjPCB.Zip 5KB minisys_S2-20190719.~(1).PcbDoc.Zip 5.43MB TFTLCD.~(1).SchDoc.Zip 5KB minisys_S4-202009.~(1).PcbDoc.Zip 7.18MB DAC.~(1).SchDoc.Zip 6KB Project Logs for minisys minisys20190712 PCB ECO 2019-7-18 15-15-07.LOG 15KB minisys20190712 PCB ECO 2019-7-18 17-50-38.LOG 0B minisys20190712 PCB ECO 2019-7-18 16-07-59.LOG 192B minisys20190712 PCB ECO 2019-7-19 10-27-21.LOG 11KB minisys20190712 PCB ECO 2019-7-18 15-52-20.LOG 314B minisys20190712 PCB ECO 2019-7-18 15-49-26.LOG 377B DC_MOTOR.SchDoc 18KB DDS98XX.SchDoc 22KB wuhanzhongxian.SchDoc 15KB POWER.SchDoc 141KB TFTLCD.SchDoc 34KB minisys_S2.PrjPCBStructure 51B MCU1.SchDoc 140KB minisys.PrjPCBStructure 51B USART.SchDoc 32KB minisys_S2.PrjPCB 44KB minisys_S4-202009.PcbDoc.htm 4KB mcu.SchDoc 203KB资源评论
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