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### 61580使用手册知识点概览 #### 一、61850标准简介 61850标准并非直接出现在本文件中，但从文件标题与描述推测，这里可能是指IEC 61850标准，这是一个关于变电站自动化系统的国际标准。而该手册实际介绍的是DDC的BU-65170、BU-61580及BU-61585 Bus Controller/Remote Terminal/Monitor Terminal (BC/RT/MT) Advanced Communication Engine (ACE) 终端，这些终端提供了一个完整的集成接口，用于连接主机处理器和MIL-STD-1553A/B或STANAG 3838总线。 #### 二、产品概述 - **产品系列**：BU-65170、BU-61580及BU-61585是DDC公司的Bus Controller/Remote Terminal/Monitor Terminal (BC/RT/MT) Advanced Communication Engine (ACE) 终端。 - **功能特点**： - 提供了完整的集成接口，用于连接主机处理器和MIL-STD-1553A/B或STANAG 3838总线。 - ACE系列采用1.9平方英寸、70针、低轮廓、共烧多芯片模块（MCM）陶瓷封装，适用于对高度有严格要求的应用场合。 - BU-61585 ACE集成了双收发器、协议处理、内存管理、处理器接口逻辑和总共12K字的RAM，可选择DIP或扁平封装。 - 支持+5V电源以及-15V或-12V电源。 - 内部RAM可以配置为12Kx16或8Kx17。 - 8Kx17 RAM特性提供了内存完整性检查的能力，通过实现所有访问的RAM奇偶校验生成和验证来实现。 - 为了最小化板空间和“胶水”逻辑，ACE提供了与主机处理器和内部/外部RAM之间接口的最大灵活性。 #### 三、高级功能架构 - **软件兼容性**：ACE终端在保持与DDC的Advanced Integrated Multiplexer (AIM) 系列混合体的软件兼容性的同时，还融入了大量的架构增强功能。 - **灵活的操作**：允许灵活操作，同时减轻主机处理器的负担，确保数据样本的一致性，并支持大量数据传输。 - **运行频率**：ACE混合体可以在12MHz或16MHz下运行。 - **线绑定选项**：允许编程RT地址（硬件固定是标准配置）和外部发射器抑制输入。 #### 四、关键特性 - **完全集成的MIL-STD-1553接口终端**：具备完全集成的MIL-STD-1553接口终端，支持标准4Kx16 RAM和可选的12Kx16或8Kx17 RAM。 - **灵活的处理器/内存接口**：提供了灵活的处理器/内存接口。 - **RAM奇偶校验生成/检查**：可选的RAM奇偶校验生成/检查功能。 - **自动BC重试**：支持自动BC重试功能。 - **可编程BC间隙时间**：支持可编程的BC间隙时间。 - **BC帧自动重复**：支持BC帧的自动重复功能。 - **灵活的RT数据缓冲**：提供了灵活的RT数据缓冲能力。 - **可编程非法化**：支持可编程非法化功能。 - **选择性消息监控**：支持选择性消息监控功能。 - **同步RT/监控模式**：支持同步RT/监控模式。 #### 五、总线接口组件 - **双收发器**：每个通道配备一个收发器。 - **多协议编码器/解码器及内存管理**：包括多协议编码器/解码器和内存管理功能。 - **RT地址共享RAM地址总线**：RT地址与共享RAM地址总线相连。 - **处理器接口**：处理器接口用于连接主机处理器和其他外部设备。 DDC的BU-65170、BU-61580及BU-61585 ACE终端提供了强大的功能和支持，非常适合于需要MIL-STD-1553A/B或STANAG 3838总线接口的复杂应用环境中。

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BU-65170/61580 and BU-61585

DESCRIPTION

DDC's BU-65170, BU-61580 and

BU-61585 Bus Controller / Remote

Terminal / Monitor Terminal

(BC/RT/MT) A d v anced

Communication Engine (ACE) termi-

nals comprise a complete integrated

interface between a host processor

and a MIL-STD-1553 A and B or

STANAG 3838 bus.

The ACE series is packaged in a 1.9 -

square-inch, 70-pin, low-profile,

cofired MultiChip Module (MCM)

ceramic package that is well suited for

applications with stringent height

requirements.

The BU-61585 ACE integrates dual

transceiver, protocol, memory man-

agement, processor interface logic,

and a total of 12K words of RAM in a

choice of DIP or flat pack packages.

The BU-61585 requires +5 V power

and either -15 V or -12 V power.

The BU-61585 internal RAM can be

configured as 12K x 16 or 8K x 17.

The 8K x 17 RAM feature provides

capability for memory integrity check-

ing by implementing RAM parity gen-

eration and verification on all access-

es. To minimize board space and

“glue” logic, the ACE provides ultimate

flexibility in interfacing to a host

processor and internal/external RAM.

The advanced functional architecture

of the ACE terminals provides soft-

ware compatibility to DDC's

Advanced Integrated Multiplexer (AIM)

series hybrids, while incorporating a

multiplicity of architectural enhance-

ments. It allows flexible operation

while off-loading the host processor,

ensuring data sample consistency,

and supports bulk data transfers.

The ACE hybrids may be operated at

either 12 or 16 MHz. Wire bond

options allow for programmable RT

address (hardwired is standard) and

external transmitter inhibit inputs.

MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,

ADVANCED COMMUNICATION ENGINE (ACE)

FEATURES

•

Fully Integrated MIL-STD-1553

Interface Terminal

•

Flexible Processor/Memory

Interface

•

Standard 4K x 16 RAM and

Optional 12K x 16 or 8K x 17 RAM

Available

•

Optional RAM Parity

Generation/Checking

•

Automatic BC Retries

•

Programmable BC Gap Times

•

BC Frame Auto-Repeat

•

Flexible RT Data Buffering

•

Programmable Illegalization

•

Selective Message Monitor

•

Simultaneous RT/Monitor Mode

TRANSCEIVER

CH. A

TRANSCEIVER

CH. B

DUAL

ENCODER/DECODER,

MULTIPROTOCOL

AND

MEMORY

MANAGEMENT

RT ADDRESS

SHARED

RAM

ADDRESS BUS

PROCESSOR

AND

MEMORY

INTERFACE

LOGIC

DATA BUS

D15-D0

A15-A0

DATA

BUFFERS

ADDRESS

BUFFERS

PROCESSOR

DATA BUS

PROCESSOR

ADDRESS BUS

MISCELLANEOUS

INCMD

CLK_IN, TAG_CLK,

MSTCLR,SSFLAG/EXT_TRG

RTAD4-RTAD0, RTADP

TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,

MSB/LSB/DTGRT

IOEN, MEMENA-OUT, READYD

ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,

8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT

PROCESSOR

AND

MEMORY

CONTROL

INTERRUPT

REQUEST

TX/RX_A

TX/RX_B

* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY

1992, 1999 Data Device Corporation

ACE User’s Guide

Also Available

FIGURE 1. ACE BLOCK DIAGRAM

Data Device Corporation

www.ddc-web.com

BU-65170/61580/61585

H1 web-09/02-0

TABLE 1. “ACE” SERIES SPECIFICATIONS

PARAMETER MIN TYP MAX UNITS

ABSOLUTE MAXIMUM RATING

Supply Voltage

! Logic +5V

! Transceiver +5V

! -15V

! -12V

Logic

! Voltage Input Range

-0.3

-18.0

-0.3

7.0

0.3

+0.3

RECEIVER

Differential Input Resistance

! (BU-65170/61580/61585X1,

BU-65170/61580/61585X2)

(Notes 1-7)

! (BU-65170/61580/61585X3,

BU-65170/61580/61585X6)

(Notes 1-7)

Differential Input Capacitance

! (BU-65170/61580/61585X1,

BU-65170/61580/61585X2)

(Notes 1-7)

! (BU-65170/61580/61585X3,

BU-65170/61580/61585X6)

(Notes 1-7)

Threshold Voltage, Transformer

Coupled, Measured on Stub

Common Mode Voltage (Note 7)

2.5

0.200

0.860

kΩ

Vp-p

Vpeak

-250

100

150

250

300

Vp-p

mVp-p,

diff

nsec

LOGIC

VIL

IIH (Vcc=5.5V, VIN=Vcc)

IH (Vcc=5.5V, VIN=2.7V)

! SSFLAG/EXT_TRIG

! All Other Inputs

IL (Vcc=5.5V, VIN=0.4V)

! SSFLAG/EXT_TRIG

! All Other Inputs

OH (Vcc=4.5V, VIH=2.7V,

IL=0.2V, IOH=max)

OL (Vcc=4.5V, VIH=2.7V,

VIL=0.2V, IOL=max)

IOL

! DB15-DB0, A15-A0, MEMOE/

ADDR_LAT, MEMWR

ZER

OWAIT, DTREQ/16/8,

ACK/POLARITY_SEL

2.0

-10

-692

-346

-794

-397

2.4

6.4

0.8

-84

-42

-100

-50

0.4

µA

5.5

-14.25

5.5

-11.4

5.5

5.25

190

108

160

255

190

120

185

305

200

350

500

800

240

108

160

255

4.5

-15.75

4.5

-12.6

4.5

4.75

POWER SUPPLY REQUIREMENTS

Voltages/Tolerances

! BU-65170/61580/61585X1

• +5V (Logic)

• +5V (Ch. A, Ch. B)

• -15V (Ch. A, Ch. B)

! BU-65170/61580/61585X2

• +5V (Logic)

• +5V (Ch. A, Ch. B)

• -12V (Ch. A, Ch. B)

! BU-65170/61580/61585X3,

BU-65170/61580/61585X6

• +5V (Logic)

• +5V (Ch. A, Ch. B)

Current Drain (Total Hybrid)

! BU-65170/61580X1

• +5V (Logic, Ch. A, Ch. B)

• -15V (Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X2

• +5V (Logic, Ch. A, Ch. B)

• -12V (Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X3,

BU-65170/61580X6

• +5V (Logic, Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X1

• +5V (Logic, Ch. A, Ch. B)

• -15V (Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

-6.4

-3.2

3.2

UNITSMAXTYPMINPARAMETER

TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)

TRANSMITTER

Differential Output Voltage

! Direct Coupled Across 35 Ω,

Measured on Bus

! Transformer Coupled Across

70 Ω, Measured on Bus

•(BU-65170/61580/61585X1)

•(BU-65170/61580/61585X2,X3, X6)

Output Noise, Differential (Direct

Coupled)

Output Offset Voltage, Transformer

Coupled Across 70 ohms

Rise/Fall Time

LOGIC (cont’d)

! INCMD, INT MEMENA_OUT,

READ

YD, IOEN, TXA, TXA,

TXB, TXB

, TX_INH_OUT_A,

TX_INH_OUT_B,

IOH

! DB15-DB0, A15-A0, MEMOE/

ADDR_LAT, MEMWR/

ZER

WAIT, DTREQ/16/8,

ACK

/POLARITY_SEL

! INCMD, INT

, MEMENA_OUT,

READ

YD, IOEN, TXA, TXA

TXB, TXB

, TX_INH_OUT_A,

TX_INH_OUT_B,

(Input Capacitance)

CIO (Bi-directional signal input

capacitance)

5.0

-15.0

5.0

-12.0

5.0

105

180

130

230

245

360

590

105

180

Data Device Corporation

www.ddc-web.com

BU-65170/61580/61585

H1 web-09/02-0

240

120

185

305

250

400

550

850

1.85

2.25

2.72

3.52

1.67

2.10

2.59

3.46

1.00

1.43

1.86

2.72

2.10

2.50

2.97

3.77

1.92

2.35

2.84

3.71

1.25

1.68

2.11

2.97

0.68

1.06

1.45

2.23

0.59

0.92

1.36

2.16

0.25

0.68

1.11

1.97

105

130

230

105

255

370

600

! BU-61585X2

• +5V (Logic, Ch. A, Ch. B)

• -12V (Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X3,

BU-61585X6

• +5V (Logic, Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

POWER DISSIPATION

Total Hybrid

! BU-65170/61580X1

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X3,

BU-65170/61580X6

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X1

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X3,

BU-61585X6

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

Hottest Die

! BU-65170/61580X1

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X3,

BU-65170/61580X6

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

UNITSMAXTYPMINPARAMETER

TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)

oz (g)0.6 (17)

in.

(mm)

in.

(mm)

1.9 X 1.0 X 0.165

(48.3 x 25.4 x 4.19)

1.9 X 1.0 X 0.150

(48.3 x 25.4 x 3.81)

PHYSICAL CHARACTERISTICS

Size

! BU-65170/61580/61585 S

! BU-65170/61580/61585 V

Weight

! BU-65170/61580/61585 S/V

°C/W

°C

6.99

6.8

150

+300

-55

-65

THERMAL

Thermal Resistance, Junction-to-Case,

Hottest Die (θJC)

! BU-65170/61580/61585X1,

BU-65170/61580/61585X2,

! BU-65170/61580/61585X3,

BU-65170/61580/61585X6

Operating Junction Temperature

Storage Temperature

Lead Temperature (soldering, 10 sec.)

MHz

µs

0.01

0.1

0.001

0.01

19.5

23.5

51.5

131

16.0

12.0

2.5

9.5

18.5

22.5

50.5

129.5

668

17.5

21.5

49.5

127

CLOCK INPUT

Frequency

! Nominal Value (programmable)

• Default Mode

• Software Programmable Option

! Long Term Tolerance

• 1553A Mode

• 1553B Mode

! Short Term Tolerance, 1 second

• 1553A Mode

• 1553B Mode

! Duty Cycle

• 16 MHz

• 12 MHz

1553 MESSAGE TIMING

Completion of CPU Write (BC Start)-

to-Start of Next Message

BC Intermessage Gap (Note 8)

BC/RT/MT Response Timeout (Note 9)

! 18.5 nominal

! 22.5 nominal

! 50.5 nominal

! 128.0 nominal

RT Response Timeout (Note 11)

Transmitter Watchdog Timeout

UNITSMAXTYPMINPARAMETER

0.68

1.06

1.45

2.23

0.59

0.92

1.36

2.16

0.25

0.68

1.11

1.97

0.335

0.600

0.860

1.385

0.290

0.590

0.890

1.490

0.200

0.630

0.885

1.395

! BU-61585X1

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X3,

BU-61585X6

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)

0.850

1.195

1.450

1.975

0.835

1.135

1.435

2.035

0.475

0.905

1.160

1.670

0.900

1.245

1.500

2.025

0.885

1.185

1.485

2.085

0.525

0.955

1.210

1.720

0.335

0.600

0.860

1.385

0.290

0.590

0.890

1.490

0.200

0.630

0.885

1.395

Data Device Corporation

www.ddc-web.com

BU-65170/61580/61585

H1 web-09/02-0

INTRODUCTION

DDC's ACE series of Integrated BC/RT/MT hybrids provide a

complete, flexible interface between a microprocessor and a

MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,

implementing Bus Controller, Remote Terminal (RT) and Monitor

Terminal (MT) modes. Packaged in a single 1.9-square-inch,

70-pin DIP or surface mountable flatpack or J-lead package, the

ACE series contains dual low-power transceivers and

encoder/decoders, complete BC/RT/MT multi-protocol logic,

memory management and interrupt logic, 4K x 16 of shared sta-

tic RAM and a direct, buffered interface to a host processor bus.

The BU-65170/61580 contains internal address latches and bidi-

rectional data buffers to provide a direct interface to a host

processor bus. The BU-65170/61580 may be interfaced directly

to both 16-bit and 8-bit microprocessors in a buffered shared

RAM configuration. In addition, the ACE may connect to a 16-bit

processor bus via a Direct Memory Access (DMA) interface. The

BU-65170/61580 includes 4K words of buffered RAM.

Alternatively, the ACE may be interfaced to as much as 64K

words of external RAM in either the shared RAM or DMA config-

urations.

The ACE RT mode is multiprotocol, supporting MIL-STD-1553A,

MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus),

and the McAir A3818, A5232, and A5690 protocols. Full compli-

ance to the McAir specs, however, requires the use of a sinu-

soidal transceiver (transceiver option 5). Refer to the BU-61590

data sheet for additional information on McAir terminals.

The memory management scheme for RT mode provides an

option for separation of broadcast data, in compliance with

1553B Notice 2. Both double buffer and circular buffer options

are programmable by subaddress. These features serve to

ensure data consistency and to off-load the host processor for

bulk data transfer applications.

The ACE series implements three monitor modes: a word moni-

tor, a selective message monitor, and a combined RT/selective

monitor. Other features include options for automatic retries and

programmable intermessage gap for BC mode, an internal Time

Tag Register, an Interrupt Status Register and internal command

illegalization for RT mode.

FUNCTIONAL OVERVIEW

TRANSCEIVERS

The transceivers in the BU-65170/61580X3(X6) are fully mono-

lithic, requiring only a +5 volt power input. Besides eliminating

the need for an additional power supply, the use of a 5 volt (only)

transceiver requires the use of step-up, rather than step-down,

isolation transformers. This provides the advantage of a higher

terminal input impedance than is possible for a 15 volt or 12 volt

transmitter. As a result, there is greater margin for the input

impedance test, mandated for 1553 validation testing. This

allows for longer cable lengths between an LRU's system con-

nector and the isolation transformers of an embedded 1553 ter-

minal.

For the +5 V and -15 V/-12 V front end, the BU-65170/

61580X1(X2) uses low-power bipolar analog monolithic and

thick-film hybrid technology. The transceiver requires +5 V and -

15 V (-12 V) only (requiring no +15 V/+12 V) and includes volt-

age source transmitters.The voltage source transmitters provide

superior line driving capability for long cables and heavy

amounts of bus loading. In addition, the monolithic transceivers

in the BU-65170/61580X1 provide a minimum stub voltage level

of 20 volts peak-to-peak transformer coupled, making them suit-

able for MIL-STD-1760 applications.

The receiver sections of the BU-65170/61580 are fully compliant

with MIL-STD-1553B in terms of front end overvoltage protec-

tion, threshold, common mode rejection, and word error rate. In

addition, the receiver filters have been designed for optimal oper-

ation with the J´ chip's Manchester II decoders.

J´ DIGITAL MONOLITHIC

The J´ digital monolithic represents the cornerstone element of

the ACE family of terminals. The development of the J´ chip rep-

resents the fifth generation of 1553 protocol and interface design

for DDC. Over the years, DDC's 1553 protocol and interface

design has evolved from: (1) discrete component sets, consisting

of multiple hybrids (with large numbers of chips inside the indi-

vidual hybrids) and programmable logic devices, to (2) multiple

custom ASICs to perform the functions of encoder/decoder and

RT protocol within a single hybrid, to (3) the BUS-61553

Advanced Integrated Mux Hybrid (AIM-HY) series, containing, in

addition to a dual monolithic/thick-film transceiver and discrete

RAM chips, a custom protocol chip and a separate custom mem-

ory management/processor interface chip, to (4) the BUS-61559

Advanced Integrated Mux Hybrids with Enhanced RT Features

(AIM-HY'er — the AIM-HY'er series includes memory manage-

ment and processor interface functions beyond those of the AIM-

HY series) , to (5) the full integration of the J´ chip.

Notes for Table 1: Notes 1 through 6 are applicable to the Receiver

Differential Resistance and Differential Capacitance specifications:

(1) Specifications include both transmitter and receiver (tied together

internally).

(2) Measurement of impedance is directly between pins TX/RX A(B)

and TX/RX A(B) of the BU-65170/61580XX hybrid.

(3) Assuming the connection of all power and ground inputs to the

hybrid.

(4) The specifications are applicable for both unpowered and powered

conditions.

(5) The specifications assume a 2 volt rms balanced, differential, sinu-

soidal input. The applicable frequency range is 75 kHz to 1 MHz.

(6) Minimum resistance and maximum capacitance parameters are

guaranteed,but not tested, over the operating range.

(7) Assumes a common mode voltage within the frequency range of dc

to 2MHz, applied to pins of the isolation transformer on the stub

side (either direct or transformer coupled), referenced to hybrid

ground. Use a DDC recommended transformer or other transformer

that provides an equivalent minimum CMRR.

(8) Typical value for minimum intermessage gap time. Under software

control, may be lengthened to (65,535µs minus message time), in

increments of 1µs.

(9) Software programmable (4 options). Includes RT-to-RT Timeout

(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT

Status).

(10) For both +5V logic and transceiver. +5V for channels A and B.

(11) Measured from mid-parity crossing of Command Word to mid-sync

crossing of RT's Status Word.

(12) Specifications for BU-65171, BU-61581, and BU-61586 are identi-

cal to the specifications for the BU-65170, BU-61580, and BU-

61585 respectively.

Data Device Corporation

www.ddc-web.com

BU-65170/61580/61585

H1 web-09/02-0

The J´ chip consists of a dual encoder/decoder, complete proto-

col for Bus Controller (BC), 1553A/B/McAir Remote Terminal

(RT), and Monitor (MT) modes; memory management and inter-

rupt logic; a flexible, buffered interface to a host processor bus

and optional external RAM; and 4K words of on-chip RAM.

Reference the region within the dotted line of FIGURE 1. Besides

realizing all the protocol, memory management, and interface

functions of the earlier AIM-HY'er series, the J´ chip includes a

large number of enhancements to facilitate hardware and soft-

ware design, and to further off-load the 1553 terminal's host

processor.

DECODERS

The default mode of operation for the BU-65170 RT and BU-

61580 BC/RT/MT requires a 16 MHz clock input. If needed, a

software programmable option allows the device to be operated

from a 12 MHz clock input. Most current 1553 decoders sample

using a 10 MHz or 12 MHz clock. In the 16 MHz mode (default

following a hardware or software reset), the ACE decoders sam-

ple 1553 serial data using the 16 MHz clock. In the 12 MHz

mode, the decoders sample using both clock edges; this pro-

vides a sampling rate of 24 MHz. The faster sampling rate for the

J´ chip’s Manchester II decoders provides superior performance

in terms of bit error rate and zero-crossing distortion tolerance.

For interfacing to fiber optic transceivers for MIL-STD-1773 appli-

cations, a transceiverless version of the J´ chip, the BU-65620,

can be used. These versions provide a pin-programmable option

for a direct interface to the single-ended outputs of a fiber optic

receiver. No external logic is needed.

TIME TAGGING

The ACE includes an internal read/writable Time Tag Register.

This register is a CPU read/writable 16-bit counter with a pro-

grammable resolution of either 2, 4, 8, 16, 32, or 64 µs per LSB.

Also, the Time Tag Register may be clocked from an external

oscillator. Another option allows software-controlled increment-

ing of the Time Tag Register. This supports self-testing for the

Time Tag Register. For each message processed, the value of

the Time Tag register is loaded into the second location of the

respective descriptor stack entry (“TIME TAG WORD”) for both

BC and RT modes.

Additional provided options will: clear the Time Tag Register fol-

lowing a Synchronize (without data) mode command or load the

Time Tag Register following a Synchronize (with data) mode

command; enable an interrupt request and a bit setting in the

Interrupt Status Register when the Time Tag Register rolls over

from 0000 to FFFF. Assuming the Time Tag Register is not

loaded or reset, this will occur at approximately 4-second time

intervals, for 64 µs/LSB resolution, down to 131 ms intervals, for

2 µs/LSB resolution.

Another programmable option for RT mode is the automatic

clearing of the Service Request Status Word bit following the

ACE's response to a Transmit Vector Word mode command.

INTERRUPTS

The ACE series components provide many programmable

options for interrupt generation and handling. The interrupt out-

put pin (INT) has three software programmable modes of oper-

ation: a pulse, a level output cleared under software control, or a

level output automatically cleared following a read of the

Interrupt Status Register.

Individual interrupts are enabled by the Interrupt Mask Register.

The host processor may easily determine the cause of the inter-

rupt by using the Interrupt Status Register. The Interrupt Status

The Interrupt Status Register may be updated in two ways. In the

standard interrupt handling mode, a particular bit in the Interrupt

Status Register will be updated only if the condition exists and

the corresponding bit in the Interrupt Mask Register is enabled.

In the enhanced interrupt handling mode, a particular bit in the

Interrupt Status Register will be updated if the condition exists

regardless of the contents of the corresponding Interrupt Mask

bit enables an interrupt for a particular condition.

ADDRESSING, INTERNAL REGISTERS, AND

MEMORY MANAGEMENT

The software interface of the BU-65170/61580 to the host

processor consists of 17 internal operational registers for normal

operation, an additional 8 test registers, plus 64K x 16 of shared

memory address space.The BU-65170/61580's 4K x 16 of inter-

nal RAM resides in this address space. Reference TABLE 2 and

24.

Definition of the address mapping and accessibility for the ACE's

17 non-test registers, and the test registers, is as follows:

Interrupt Mask Register is used to enable and disable interrupt

requests for various conditions.

Configuration Registers #1 and #2 are used to select the BU-

61580's mode of operation, and for software control of RT Status

Word bits, Active Memory Area, BC Stop-on-Error, RT Memory

Management mode selection, and control of the Time Tag oper-

ation.

Start/Reset Register is used for “command” type functions,

such as software reset, BC/MT Start, Interrupt Reset, Time Tag

Reset, and Time Tag Register Test. The Start/Reset Register

includes provisions for stopping the BC in its auto-repeat mode,

either at the end of the current message or at the end of the cur-

rent BC frame.

BC/RT Command Stack Pointer Register allows the host CPU

to determine the pointer location for the current or most recent

message when the BU-61580 is in BC or RT modes.

BC Control Word/RT Subaddress Control Word Register:In

BC mode, it allows host access to the current, or most recent BC

Control Word. The BC Control Word contains bits that select the

active bus and message format, enable off-line self-test, mask-

ing of Status Word bits, enable retries and interrupts, and spec-

ify MIL-STD-1553A or -1553B error handling. In RT mode, this

Subaddress Control Word. The Subaddress Control Word is

used to select the memory management scheme and enable

interrupts for the current message. The read/write accessibility

can be used as an aid for testing the ACE.

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tyyhaha

2011-09-13

呃，这不就是网上直接下载的datasheet嘛，还害我浪费计分
nudtfzj

2012-09-09

就是网上的datasheet，不过很感谢共享

my1111ym

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