LPC1769_68_67_66_65_64_63.pdf

1. General description

The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for

embedded applications featuring a high level of integration and low power consumption.

The ARM Cortex-M3 is a next generation core that offers system enhancements such as

enhanced debug features and a higher level of support block integration.

The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The

LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU

2

2

S-bus interface,

8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface,

four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time

Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.

The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x

 ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

 On-chip SRAM includes:

 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU

access.

LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

memory-to-memory transfers.

 Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

delays.

 Split APB bus allows high throughput with few stalls between the CPU and DMA.

.)

 Four UARTs with fractional baud rate generation, internal FIFO, and DMA support.

One UART has modem control I/O and RS-485/EIA-485 support, and one UART

 CAN 2.0B controller with two channels. (Not available on all parts, see Table 2

.)

 SPI controller with synchronous, serial, full duplex communication and

programmable data length.

 Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces

C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard

port pins. Enhancements include multiple address recognition and monitor mode.

 I

2

2

2

input/output. (Not available on all parts, see Table 2

 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,

conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can

 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA

 Four general purpose timers/counters, with a total of eight capture inputs and ten

compare outputs. Each timer block has an external count input. Specific timer

events can be selected to generate DMA requests.

LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

 ARM Cortex-M3 system tick timer, including an external clock input option.

 Repetitive interrupt timer provides programmable and repeating timed interrupts.

 Each peripheral has its own clock divider for further power savings.

 Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire

Debug and Serial Wire Trace Port options.

 Emulation trace module enables non-intrusive, high-speed real-time tracing of

 Integrated PMU (Power Management Unit) automatically adjusts internal regulators to

minimize power consumption during Sleep, Deep sleep, Power-down, and Deep

power-down modes.

 The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from

any priority interrupt that can occur while the clocks are stopped in deep sleep,

Power-down, and Deep power-down modes.

 Processor wake-up from Power-down mode via any interrupt able to operate during

 Brownout detect with separate threshold for interrupt and forced reset.

 Power-On Reset (POR).

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 Code Read Protection (CRP) with different security levels.

 Unique device serial number for identification purposes.

 Available as LQFP100 (14 mm  14 mm  1.4 mm) and TFBGA100

LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.

5. Block diagram