1.1 Introduction
1.2 SMBus Protocols
SLAA249 – April 2005
Implementing SMBus using MSP430 Hardware I2C
Harman Grewal ................................................................................................................. MSP430
This application report describes the implementation of the system management bus
(SMBus) using the MSP430 hardware I2C peripheral. SMBus is used as a communi-
cation link for smart batteries, power related devices and a wide variety of other system
devices. This report includes the support for master and slave protocols in a SMBus
communication system.
SMBus is a two-wire serial interface based on the principles of I
2
C. The two lines are serial clock (SCL)
and serial data (SDA) which are tied to V
CC
using pull-up resistors. The devices communicating on this
bus can drive the lines low or release them to high impedance. This connection is a wired-AND
configuration. Multiple I
2
C/SMBus devices can be connected on the bus, but MSP430 pins should not be
pulled above V
CC
. For example, if the V
CC
of the MSP430 is at 3V, then all devices on the bus must be
pulled up to only 3V.
A device performing data transfers on the bus can be considered as a master or a slave. Each master and
slave device can either be a transmitter (send data) or a receiver (receive data), and the communication
on the bus is always initiated by the master by providing a valid start condition and the SCL signal.
Multiple master and slave devices may be connected on the bus, but only one device may master the bus
during a data transfer. Since more than one master may simultaneously attempt to take control of the bus
and start a transmission, the I
2
C/SMBus protocol provides an arbitration mechanism which relies on the
wired-AND connection of all devices to the bus. A master device that generates a logic high on the SDA
bus loses arbitration to a master that generates a logic low on the data bus. The MSP430 master
transmitter that loses arbitration switches to slave receiver mode and sets the arbitration lost flag, ALIFG
[1]. Each device on the bus has a unique 7-bit address, which allows a total of 128 devices to be
connected on the bus. Some addresses are dedicated SMBus addresses which are reserved and must
not be assigned to any SMBus device. For instance the SMBus Alert response address (0001 100b) [2].
The different communication protocols can be found in the System Management Bus specification [2]. The
communication always begins with a valid start condition from the master followed by a 7-bit slave
address and the read/write bit which defines the master as a receiver /transmitter respectively, except in
the quick command protocol. In quick command protocol, the read/write bit is used to turn a device on/off
or enable/disable a low power mode. The read/write bit is followed by an Acknowledge from the slave.
This is followed by 8-bit transfers which may be data, command or Packet Error Check (PEC). An
acknowledge is sent by the receiver after each byte is received. To end the transfer, a valid stop condition
is initiated by the master.
The SMBus standard introduced the Packet Error Checking (PEC) mechanism to improve communication
reliability. The PEC is a CRC-8 error check byte, calculated on all message bytes except the ACK, NACK,
START and STOP bits. The PEC is added to the message by the transmitter. The PEC in this application
report is calculated using a cyclic redundancy check (CRC-8) polynomial, C(x) = x
8
+ x
2
+ x
1
+ 1 and is
calculated bit by bit in the order of bits received. Refer to SMBus specification for details on the PEC.
Implementing SMBus using MSP430 Hardware I
2
CSLAA249 – April 2005 1
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