library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity run_led is
Port ( clk : in STD_LOGIC;
rst_n : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end run_led;
architecture Behavioral of run_led is
signal counter:STD_LOGIC_VECTOR(26 downto 0);
signal cnt:STD_LOGIC_VECTOR(2 downto 0);
begin
process(clk,rst_n)
begin
if(rst_n='0') then
counter<="000000000000000000000000000";
elsif(clk'event and clk='1') then
counter<=counter+1;
end if;
end process;
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