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MT7628编程指南.pdf
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MT7628编程指南,寄存器手册
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loginid=adamchien@synnex.com.tw,time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
Version: 1.0
Release date: 2014-06-03
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MT7628
PROGRAMMING GUIDE
loginid=adamchien@synnex.com.tw,time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Chip Name
Confidential B
MediaTek Confidential © 2014 MediaTek Inc. Page 2 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
MT7628 PROGRAMMING GUIDE
MT7628 Overview
The MT7628 SoC includes a high performance 580/575 MHz MIPS24KEc CPU core and high speed USB2.0/PCIe
interfaces, which is designed to enable a multitude of high performance, cost-effective IEEE 802.11n
applications with a MediaTek WiFi client card.
Functional Block Diagram
MIPS 24KEc
64KB I-Cache
32KB D-Cache
(580/575MHz)
OCP Bridge
OCP_IF
2ch Arbiter
DDR1/DDR2
Memory Controller
8ch QoS Arbiter
RBUS (SYS_CLK)
Rbus
SPI(M) x2
APB BUS
GDMA
RJ45 x5
Switch
5-Port EPHY
WPDMA
PCIe 1.1
Host
Controller
PCIe 1.1 PHY
USB 2.0
Host
Controller
USB 2.0 PHY
UTMI
PCIe Host
GPIO
PCM
I2S
I2C
I2S
UARTL x3
APB BUS
INTC
I2C
GPIO
UART
SPI
To CPU
interrupts
16-Bit
DDR1/DDR2
DDR PHY
EJTAG
CLKGEN
RSTGEN
PLLs & SSC
IOMUX
Strap Pin
PADRING
MT7628 Block Diagram
MAC
WLAN
BBP
RF 11n 2x2
2.4GHz
SUTIF
3wSPI
PCM
PDMA
USB Host
AES
Engine
SDXC
eMMC
PIPE
PWM x4 PWM
SPI(S) SPI
Timer
SDXC
Host
Figure 1-1 MT7628 Block Diagram
There are several masters (MIPS 24KEc, USB, PCI Express, SDXC, FE) in the MT7628 SoC on a high performance,
low latency Rbus. In addition, the MT7628 SoC supports lower speed peripherals such as UART Lite, GPIO, I2C
and SPI via a low speed peripheral bus (Pbus). The DDR/DDR2 controller is the only bus slave on the Rbus. It
includes an Advanced Memory Scheduler to arbitrate the requests from bus masters, enhancing the
performance of memory access intensive tasks.
loginid=adamchien@synnex.com.tw,time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Chip Name
Confidential B
MediaTek Confidential © 2014 MediaTek Inc. Page 3 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
MT7628 PROGRAMMING GUIDE
Document Revision History
Revision Date Author Description
1.0 2014-04-28 PeterCT Wu Initial Draft
loginid=adamchien@synnex.com.tw,time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Chip Name
Confidential B
MediaTek Confidential © 2014 MediaTek Inc. Page 4 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
MT7628 PROGRAMMING GUIDE
Table of Contents
MT7628 OVERVIEW 2
FUNCTIONAL BLOCK DIAGRAM 2
DOCUMENT REVISION HISTORY
3
TABLE OF CONTENTS 4
TABLE OF FIGURES 6
LIST OF TABLES 7
1. MIPS 24KEC PROCESSOR 8
1.1 FEATURES 8
1.2 BLOCK DIAGRAM 9
1.3 MEMORY MAP SUMMARY 10
1.3 INTERUPT TABLE SUMMARY 11
1.4 CLOCK PLAN 12
2. REGISTERS 13
2.1 NOMENCLATURE 13
2.2 SYSTEM CONTROL 14
2.2.1 FEATURES 14
2.2.2 BLOCK DIAGRAM 14
2.2.3 REGISTERS 15
2.3 TIMER 32
2.3.1 FEATURES 32
2.3.2 BLOCK DIAGRAM 32
2.3.3 REGISTERS 33
2.4 INTERRUPT CONTROLLER 38
2.4.1 REGISTERS 38
2.5 EMC CONTROLLER 46
2.5.1 REGSITER 46
2.6 R-BUS CONTROLLER 63
2.6.1 FEATURES 63
2.6.2 BLOCK DIAGRAM 63
2.7 MIPS CNT 74
2.7.1 REGISTERS 74
2.8 GENERAL PURPOSE IO 76
2.8.1 FEATURES 76
2.8.2 BLOCK DIAGRAM 76
2.8.3 GPIO PIN MAPPING 77
2.8.4 REGISTER 77
2.9 SPI SLAVE 91
2.9.1 SPI SLAVE CONTROL 91
2.9.2 REGSITERS 93
2.10 I
2
C CONTROLLER 96
2.10.1 FEATURES 96
2.10.2 LIST OF REGISTERS 96
2.11 I2S CONTROLLER 103
2.11.1 FEATURES 103
2.11.2 BLOCK DIAGRAM 103
2.11.3 REGISTERS 104
loginid=adamchien@synnex.com.tw,time=2014-12-05 11:55:47,ip=58.250.71.129,doctitle=MT7628_ProgrammingGuide_20140428(E2).docx,company=Synnex Electronics HK Limited 聯強電子_RLT
MT7628
Chip Name
Confidential B
MediaTek Confidential © 2014 MediaTek Inc. Page 5 of 347
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
MT7628 PROGRAMMING GUIDE
2.12 SPI CONTROLLER 110
2.12.1 FEATURES 110
2.12.2 BLOCK DIAGRAM 110
2.12.3 REGISTERS 110
2.13 UART LITE 121
2.13.1 FEATURES 121
2.13.2 REGISTERS 121
2.14 PCM CONTROLLER 135
2.14.1 FEATURES 135
2.14.2 BLOCK DIAGRAM 135
2.14.3 LIST OF REGISTERS 136
2.14.4 PCM CONFIGURATION 136
2.14.5 REGISTER 138
2.15 GENERIC DMA CONTROLLER 155
2.15.1 FEATURES 155
2.15.2 BLOCK DIAGRAM 155
2.15.3 PERIPHERAL CHANNEL CONNECTION 155
2.15.4 REGISTERS 156
2.16 AES CONTROLLER 204
2.16.1 REGISTERS 204
2.17 PWM (PULSE WIDTH MODULATION) 214
2.17.1 REGISTERS 214
2.18 FRAME ENGINE 232
2.18.1 REGISTERS 232
2.19 SWITCH CONTROLLER 251
2.19.1 REGISTERS 251
2.20 MSDC 301
2.20.1 REGISTERS 301
2.21 PCI EXPRESS 328
2.21.1 REGISTERS 328
2.22 USB HOST CONTROLLER 336
2.22.1 REGISTERS 336
3. LIST 345
剩余346页未读,继续阅读
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