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User’s Manual
V1.2 2009-07
Microcontrollers
16/32-Bit
Architecture
XC2300B Derivatives
16/32-Bit Single-Chip Microcontroller
with 32-Bit Performance
XC2000 Family / Value Line
Edition 2009-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
User’s Manual
V1.2 2009-07
Microcontrollers
16/32-Bit
Architecture
XC2300B Derivatives
16/32-Bit Single-Chip Microcontroller
with 32-Bit Performance
XC2000 Family / Value Line
XC2300B Derivatives
XC2000 Family / Value Line
User’s Manual V1.2, 2009-07
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
XC2300B User’s Manual
Revision History: V1.2 2009-07
Previous Version(s):
V1.1 2009-04
V1.0 2008-12
Page Subjects (major changes since last revision)
2-1 Removed the configuration information for ADC and MultiCAN from block
diagram.
8-213 Notes to handle RAMs with ECC enabled: initialize RAM and clear an ECC
error
8-219 Table with further protected registers added
9-2 More detailed information on ESR pad connection.
9-28 Added information on pull devices on DAP/JTAG and ESR in pinning list
11-14 Clarified the EBCMODx registers dependency from selected boot
configuration
11-20 Moved the port assignments for EXTBUS mode from architecture to EBC
Implementation chapter
13-12 Software sequence to prepare ECC/Parity usage extended
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
User’s Manual L-1 V1.2, 2009-07
XC2300B Derivatives
XC2000 Family / Value Line
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L-1
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 System Core Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.1 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.2 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.3 Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . . . 2-8
2.2.4 Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3 On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.1 Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.2 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.4 On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.7 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3 Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4 Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.1 Program/Data SRAM (PSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.4.2 Non-Volatile Program Memory (Flash) . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.5 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.6 Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.7 IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.8 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.9 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.10 Embedded Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.10.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.10.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.10.2.1 Standard Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.10.2.2 Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.10.2.3 Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.10.3 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.10.3.1 Instruction Fetch from Flash Memory . . . . . . . . . . . . . . . . . . . . . . 3-24
3.10.3.2 Data Reads from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Table of Contents
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