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知名大学的fpga实验教程,详细描述了如何用fpga来实现fir滤波器,挺好
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EECS150 Fall 2013 Lab 3
1
Lab 3: Simulation and Testing
University of California, Berkeley
Department of Electrical Engineering and Computer Sciences
EECS150 Components and Design Techniques for Digital Systems
Ronald Fearing, Austin Buchan, Stephen Twigg
Due October 3
rd
, 2013
Table of Contents
0 Introduction ......................................................................................................................................................... 1
1 Prelab .................................................................................................................................................................... 2
2 Lab Procedure ................................................................................................................................................... 2
2.1 Relevance to Your Final Project ...................................................................................................... 2
2.2 Functional Specification .................................................................................................................. 3
2.3 Lab Resources ......................................................................................................................................... 4
2.4 Testing the Design.................................................................................................................................. 4
2.4.1 Verilog Testbench .......................................................................................................................... 4
2.4.2 Test Vector Testbench ................................................................................................................. 5
2.4.3 Writing Test Vectors ...................................................................................................................... 5
2.5 Using Modelsim ....................................................................................................................................... 6
2.6 Viewing Waveforms ............................................................................................................................... 7
3 Checkoff ............................................................................................................................................................ 10
0 Introduction
In this lab, you will learn how to simulate your modules and test them in software before pushing them to
the board. In the previous labs, you had to push your code through the entire tool chain and impact the bit
stream onto the FPGA before you could verify that your design worked.
This is feasible for simple designs that can quickly be synthesized and quickly verified on the board, but
this approach does not scale. Here we will cover how to simulate a hardware design and write test
benches, both of which are essential in the verification process of large and complex systems.
We will also be introducing the Finite Impulse-Response (FIR) filter, which will be a versatile component
of the project SIFT tracking implementation. We will examine a modular design by chaining together
Multiply ACumulate (MAC) units that in practice will synthesize to specialized DSP logic in an FPGA.
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