JEDEC Standard No. 21C
Page 4.20.21-5
Revision 1.0 Release 22
3 Pinout and Description
Table 3 — Pin Description
Pin Name Description
Num-
ber
Pin Name Description
Num-
ber
CK0_t Clock Input, positive line 1
ODT[1:0]
On Die Termination Inputs 2
CK0_c Clock Input, negative line 1 DQ[63:0] Data Input/Output 64
CK1_t Clock Input, positive line 1 CB[7:0] Data check bits Input/Output 8
CK1_c Clock Input, negative line 1 DQS_t[8:0] Data strobes 9
CKE[1:0] Clock Enables 2 DQS_c[8:0] Data strobes, negative line 9
RAS_n Row Address Strobe 1 DM[8:0]
Data Masks / Data strobes,
Termination data strobes
9
CAS_n Column Address Strobe 1
WE_n Write Enable 1
S_n[3:0] Chip Selects 4 EVENT_n
Reserved for optional hardware
temperature sensing
1
A[9:0],A11,
A[15:13]
Address Inputs 14
A10/AP Address Input/Autoprecharge 1 RESET_n Register and SDRAM control pin 1
A12/BC_n Address Input/Burst chop 1
V
DD
Power Supply xx
BA[2:0] SDRAM Bank Addresses 3
V
SS
Ground xx
SCL Serial Presence Detect (SPD) Clock Input 1
V
REFDQ
Reference Voltage for DQ 1
SDA SPD Data Input/Output 1
V
REFCA
Reference Voltage for CA 1
SA[1:0] SPD Address Inputs 2
V
TT
Termination Voltage 2
Par_In Parity bit for the Address and Control bus 1
V
DDSPD
SPD Power 1
Err_Out_n
Parity error found on the Address and
Control bus
1
Total
204
Table 4 — Registered DIMM Input/Output Functional Description
Symbol Type Polarity Function
CK0_t IN
Positive
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock
Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM).
CK0_c IN
Negative
Edge
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM Clock
Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM).
CK1_t IN
Positive
Edge
Positive line of a secondary differential pair of system clock inputs. Terminated but not used on 72b-
SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 of 72b-SO-DIMMs.
CK1_c IN
Negative
Edge
Negative line of a secondary differential pair of system clock inputs. Terminated but not used on
72b-SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 of 72b-SO-DIMMs.
ix19822015-07-04不错,有用~ jedec的规范
