MSP430F5438串口通信

//***************************************************************************** // MSP430F54x Demo - FLL+, Output 32kHz Xtal + HF Xtal + Internal DCO // // Description: This program demonstrates using an external 32kHz crystal to // supply ACLK, and using a high speed crystal or resonator to supply SMCLK. // MLCK for the CPU is supplied by the internal DCO. The 32kHz crystal // connects between pins Xin and Xout. The high frequency crystal or // resonator connects between pins XT2IN and XT2OUT. The DCO clock is // generated internally and calibrated from the 32kHz crystal. ACLK is // brought out on pin P11.0, SMCLK is brought out on P11.2, and MCLK is // brought out on pin P11.1. // ACLK = LFXT1 = 32768Hz, MCLK = default DCO = 32 x ACLK = 1048576Hz // SMCLK = HF XTAL // //* An external watch crystal between XIN & XOUT is required for ACLK *// // // NOTE: External matching capacitors must be added for the high // speed crystal or resonator as required. // // MSP430F5438 // ----------------- // /|\ | XIN|- // | | | 32kHz // ---|RST XOUT|- // | | // | | // | XT2IN|- // | | HF XTAL or Resonator (add capacitors) // | XT2OUT|- // | | // | P11.0|--> ACLK = 32kHz Crystal Out // | | // | P11.2|--> SMCLK = High Freq Xtal or Resonator Out // | | // | P11.1|--> MCLK = Default DCO Frequency // | | // | | // // W. Goh // Texas Instruments Inc. // February 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "msp430x54x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P11DIR = BIT2 + BIT1 + BIT0; // P11.2,1,0 to output direction P11SEL = BIT2 + BIT1 + BIT0; // P11.2 to output SMCLK, P11.1 // to output MCLK and P11.0 to // output ACLK P5SEL |= 0x0C; // Port select XT2 P7SEL |= 0x03; // Port select XT1 UCSCTL6 &= ~(XT1OFF + XT2OFF); // Set XT1 & XT2 On UCSCTL6 |= XCAP_3; // Internal load cap // Loop until XT1,XT2 & DCO stabilizes do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to // expected frequency UCSCTL4 |= SELA_0 + SELS_5; // Select SMCLK, ACLK source and DCO source while(1); // Loop in place }