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Intel多处理器规范
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Intel多处理器规范,包括Intel多处理器体系结构,APIC高级可编程中断控制器(82489DX),多处理器配置等
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MultiProcessor
Specification
Version 1.4
May
1997
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY
OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING
OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
A license is hereby granted to copy and reproduce this specification for internal use only.
No other license, express or implied, by estoppel or otherwise, to any other intellectual property rights is granted herein.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to implementation of information in
this specification. Intel does not warrant or represent that such implementation(s) will not infringe such rights.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products.
* Third-party trademarks are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Center
P.O. Box 7641
Mt. Prospect IL 60056-7641
or call 800-879-4683
printed on
recycled paper
Copyright 1993-1997
. Intel Corporation, All Rights Reserved.
iii
Revision History
Revision Revision History Date
Pre-release Version 1.0. Formerly called “PC+MP Specification” 10/27/93
-001 Version 1.1. Resolves conflicts with MCA-based systems. The following
changes have been made:
1. Two MP feature information bytes were moved from the BIOS System
Configuration Table to the RESERVED area of the MP Floating Pointer
Structure.
2. If the MP Floating Pointer Structure is present, it indicates that the system
is MP-compliant, in accordance with this specification. (Previously, this was
indicated by bit 0 of MP Feature Information Byte 1.)
3. One more hardware default system configuration was added for MCA+PCI
with the integrated APIC.
4/11/94
-002 Minor technical corrections. 6/1/94
-003 Added Appendix D: Multiple I/O APIC Multiple PCI Bus Systems. 9/1/94
-004 Version 1.4. Added extended configuration table to improve support for
multiple PCI bus configurations and improve future expandability. Made
clarifications to Appendix B.
7/1/95
-005 Added Appendix E: Errata. Includes information for hierarchical PCI bus. 08/15/96
-006 Appendix E Update. Included Byte 2, Bit 6 information to MP Floating Point
Structure section (4.1).
05/12/97
v
Table of Contents
Chapter 1 Introduction
1.1 Goals ........................................................................................................ 1-1
1.2 Features of the Specification .................................................................... 1-2
1.3 Scope........................................................................................................ 1-2
1.4 Target Audience ....................................................................................... 1-3
1.5 Organization of This Document ................................................................ 1-3
1.6 Conventions Used in This Document ....................................................... 1-4
1.7 For More Information................................................................................ 1-4
Chapter 2 System Overview
2.1 Hardware Overview .................................................................................. 2-2
2.1.1 System Processors...................................................................... 2-2
2.1.2 Advanced Programmable Interrupt Controller ............................. 2-3
2.1.3 System Memory........................................................................... 2-4
2.1.4 I/O Expansion Bus ....................................................................... 2-4
2.2 BIOS Overview ......................................................................................... 2-5
2.3 Operating System Overview..................................................................... 2-5
Chapter 3 Hardware Specification
3.1 System Memory Configuration ................................................................. 3-1
3.2 System Memory Cacheability and Shareability......................................... 3-2
3.3 External Cache Subsystem ...................................................................... 3-4
3.4 Locking ..................................................................................................... 3-4
3.5 Posted Memory Write ............................................................................... 3-5
3.6 Multiprocessor Interrupt Control ............................................................... 3-5
3.6.1 APIC Architecture ........................................................................ 3-5
3.6.2 Interrupt Modes............................................................................ 3-6
3.6.2.1 PIC Mode...................................................................... 3-7
3.6.2.2 Virtual Wire Mode ......................................................... 3-9
3.6.2.3 Symmetric I/O Mode ................................................... 3-11
3.6.3 Assignment of System Interrupts to the APIC Local Unit........... 3-12
3.6.4 Floating Point Exception Interrupt.............................................. 3-12
3.6.5 APIC Memory Mapping.............................................................. 3-12
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- shenxinshan6211072012-11-30资料不错,只是老了一点,有学习价值。
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