// PART OF THE MACHINE SIMULATION. DO NOT CHANGE.
package nachos.machine;
import nachos.security.*;
/**
* The <tt>Processor</tt> class simulates a MIPS processor that supports a
* subset of the R3000 instruction set. Specifically, the processor lacks all
* coprocessor support, and can only execute in user mode. Address translation
* information is accessed via the API. The API also allows a kernel to set an
* exception handler to be called on any user mode exception.
*
* <p>
* The <tt>Processor</tt> API is re-entrant, so a single simulated processor
* can be shared by multiple user threads.
*
* <p>
* An instance of a <tt>Processor</tt> also includes pages of physical memory
* accessible to user programs, the size of which is fixed by the constructor.
*/
public final class Processor {
/**
* Allocate a new MIPS processor, with the specified amount of memory.
*
* @param privilege encapsulates privileged access to the Nachos
* machine.
* @param numPhysPages the number of pages of physical memory to
* attach.
*/
public Processor(Privilege privilege, int numPhysPages) {
System.out.print(" processor");
this.privilege = privilege;
privilege.processor = new ProcessorPrivilege();
Class<?> clsKernel = Lib.loadClass(Config.getString("Kernel.kernel"));
Class<?> clsVMKernel = Lib.tryLoadClass("nachos.vm.VMKernel");
usingTLB =
(clsVMKernel != null && clsVMKernel.isAssignableFrom(clsKernel));
this.numPhysPages = numPhysPages;
for (int i=0; i<numUserRegisters; i++)
registers[i] = 0;
mainMemory = new byte[pageSize * numPhysPages];
if (usingTLB) {
translations = new TranslationEntry[tlbSize];
for (int i=0; i<tlbSize; i++)
translations[i] = new TranslationEntry();
}
else {
translations = null;
}
}
/**
* Set the exception handler, called whenever a user exception occurs.
*
* <p>
* When the exception handler is called, interrupts will be enabled, and
* the CPU cause register will specify the cause of the exception (see the
* <tt>exception<i>*</i></tt> constants).
*
* @param exceptionHandler the kernel exception handler.
*/
public void setExceptionHandler(Runnable exceptionHandler) {
this.exceptionHandler = exceptionHandler;
}
/**
* Get the exception handler, set by the last call to
* <tt>setExceptionHandler()</tt>.
*
* @return the exception handler.
*/
public Runnable getExceptionHandler() {
return exceptionHandler;
}
/**
* Start executing instructions at the current PC. Never returns.
*/
public void run() {
Lib.debug(dbgProcessor, "starting program in current thread");
registers[regNextPC] = registers[regPC] + 4;
Machine.autoGrader().runProcessor(privilege);
Instruction inst = new Instruction();
while (true) {
try {
inst.run();
}
catch (MipsException e) {
e.handle();
}
privilege.interrupt.tick(false);
}
}
/**
* Read and return the contents of the specified CPU register.
*
* @param number the register to read.
* @return the value of the register.
*/
public int readRegister(int number) {
Lib.assertTrue(number >= 0 && number < numUserRegisters);
return registers[number];
}
/**
* Write the specified value into the specified CPU register.
*
* @param number the register to write.
* @param value the value to write.
*/
public void writeRegister(int number, int value) {
Lib.assertTrue(number >= 0 && number < numUserRegisters);
if (number != 0)
registers[number] = value;
}
/**
* Test whether this processor uses a software-managed TLB, or single-level
* paging.
*
* <p>
* If <tt>false</tt>, this processor directly supports single-level paging;
* use <tt>setPageTable()</tt>.
*
* <p>
* If <tt>true</tt>, this processor has a software-managed TLB;
* use <tt>getTLBSize()</tt>, <tt>readTLBEntry()</tt>, and
* <tt>writeTLBEntry()</tt>.
*
* <p>
* Using a method associated with the wrong address translation mechanism
* will result in an assertion failure.
*
* @return <tt>true</tt> if this processor has a software-managed TLB.
*/
public boolean hasTLB() {
return usingTLB;
}
/**
* Get the current page table, set by the last call to setPageTable().
*
* @return the current page table.
*/
public TranslationEntry[] getPageTable() {
Lib.assertTrue(!usingTLB);
return translations;
}
/**
* Set the page table pointer. All further address translations will use
* the specified page table. The size of the current address space will be
* determined from the length of the page table array.
*
* @param pageTable the page table to use.
*/
public void setPageTable(TranslationEntry[] pageTable) {
Lib.assertTrue(!usingTLB);
this.translations = pageTable;
}
/**
* Return the number of entries in this processor's TLB.
*
* @return the number of entries in this processor's TLB.
*/
public int getTLBSize() {
Lib.assertTrue(usingTLB);
return tlbSize;
}
/**
* Returns the specified TLB entry.
*
* @param number the index into the TLB.
* @return the contents of the specified TLB entry.
*/
public TranslationEntry readTLBEntry(int number) {
Lib.assertTrue(usingTLB);
Lib.assertTrue(number >= 0 && number < tlbSize);
return new TranslationEntry(translations[number]);
}
/**
* Fill the specified TLB entry.
*
* <p>
* The TLB is fully associative, so the location of an entry within the TLB
* does not affect anything.
*
* @param number the index into the TLB.
* @param entry the new contents of the TLB entry.
*/
public void writeTLBEntry(int number, TranslationEntry entry) {
Lib.assertTrue(usingTLB);
Lib.assertTrue(number >= 0 && number < tlbSize);
translations[number] = new TranslationEntry(entry);
}
/**
* Return the number of pages of physical memory attached to this simulated
* processor.
*
* @return the number of pages of physical memory.
*/
public int getNumPhysPages() {
return numPhysPages;
}
/**
* Return a reference to the physical memory array. The size of this array
* is <tt>pageSize * getNumPhysPages()</tt>.
*
* @return the main memory array.
*/
public byte[] getMemory() {
return mainMemory;
}
/**
* Concatenate a page number and an offset into an address.
*
* @param page the page number. Must be between <tt>0</tt> and
* <tt>(2<sup>32</sup> / pageSize) - 1</tt>.
* @param offset the offset within the page. Must be between <tt>0</tt>
* and
* <tt>pageSize - 1</tt>.
* @return a 32-bit address consisting of the specified page and offset.
*/
public static int makeAddress(int page, int offset) {
Lib.assertTrue(page >= 0 && page < maxPages);
Lib.assertTrue(offset >= 0 && offset < pageSize);
return (page * pageSize) | offset;
}
/**
* Extract the page number component from a 32-bit address.
*
* @param address the 32-bit address.
* @return the page number component of the address.
*/
public static int pageFromAddress(int address) {
return (int) (((long) address & 0xFFFFFFFFL) / pageSize);
}
/**
* Extract the offset component from an address.
*
* @param address the 32-bit address.
* @return the offset component of the address.
*/
public static int offsetFromAddress(int address) {
return (int) (((long) address & 0xFFFFFFFFL) % pageSize);
}
private void finishLoad() {
delayedLoad(0, 0, 0);
}
/**
* Translate a virtual address into a physical address, using either a
* page table or a TLB. Check for alig
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Nachos-java源代码
共142个文件
java:62个
c:22个
o:22个
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2011-11-07
12:44:36
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Nachos-java源代码 (142个子文件)
libnachos.a 15KB
sh.c 4KB
printf.c 3KB
sort.c 965B
matmult.c 802B
readline.c 670B
mv.c 606B
cp.c 589B
halt.c 541B
cat.c 436B
strncmp.c 284B
stdio.c 281B
rm.c 278B
strcat.c 254B
strcmp.c 236B
strcpy.c 225B
strlen.c 219B
atoi.c 216B
echo.c 201B
memcpy.c 159B
assert.c 154B
memset.c 145B
stdlib.c 21B
sh.coff 10KB
mv.coff 7KB
cp.coff 7KB
cat.coff 7KB
rm.coff 7KB
echo.coff 7KB
sort.coff 3KB
matmult.coff 3KB
halt.coff 2KB
nachos.conf 555B
nachos.conf 516B
nachos.conf 455B
nachos.conf 372B
syscall.h 10KB
va-mips.h 10KB
stdarg.h 6KB
stdio.h 1KB
stdlib.h 1006B
package.html 131B
package.html 128B
package.html 107B
package.html 93B
package.html 89B
package.html 77B
package.html 69B
Processor.java 35KB
Lib.java 19KB
Machine.java 15KB
ElevatorBank.java 15KB
UserProcess.java 14KB
TCB.java 13KB
KThread.java 12KB
ElevatorGui.java 9KB
NetworkLink.java 9KB
NachosSecurityManager.java 7KB
AutoGrader.java 7KB
PriorityScheduler.java 7KB
Config.java 7KB
Interrupt.java 6KB
CoffSection.java 6KB
Privilege.java 6KB
Scheduler.java 5KB
RiderControls.java 5KB
StubFileSystem.java 4KB
Coff.java 4KB
OpenFile.java 4KB
ThreadQueue.java 4KB
Condition.java 4KB
StandardConsole.java 3KB
PostOffice.java 3KB
Packet.java 3KB
SynchConsole.java 3KB
ElevatorTest.java 3KB
MailMessage.java 3KB
Stats.java 3KB
ElevatorControls.java 3KB
UserKernel.java 3KB
NetKernel.java 2KB
Semaphore.java 2KB
ThreadedKernel.java 2KB
BoatGrader.java 2KB
Timer.java 2KB
RoundRobinScheduler.java 2KB
RiderInterface.java 2KB
Lock.java 2KB
TranslationEntry.java 2KB
Rider.java 2KB
Boat.java 2KB
SynchList.java 2KB
VMProcess.java 2KB
UThread.java 2KB
ElevatorControllerInterface.java 2KB
Alarm.java 2KB
Condition2.java 2KB
SerialConsole.java 1KB
FileSystem.java 1KB
LotteryScheduler.java 1KB
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