stm32 官方时钟配置工具

/** ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team * @version V1.1.0 * @date 27-March-2024 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * This file contains the system clock configuration for STM32F4xx devices, * and is generated by the clock configuration tool * stm32f4xx_Clock_Configuration_V1.1.0.xls * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * and Divider factors, AHB/APBx prescalers and Flash settings), * depending on the configuration made in the clock xls tool. * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the HSI (16 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() * function will do nothing and HSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or * through PLL, and you are using different crystal you have to adapt the HSE * value to your own configuration. * * 5. This file configures the system clock as follows: *============================================================================= *============================================================================= * Supported STM32F40xx/41xx/427x/437x devices *----------------------------------------------------------------------------- * System Clock source | PLL (HSE) *----------------------------------------------------------------------------- * SYSCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 8 *----------------------------------------------------------------------------- * APB2 Prescaler | 2 *----------------------------------------------------------------------------- * HSE Frequency(Hz) | 8000000 *----------------------------------------------------------------------------- * PLL_M | 8 *----------------------------------------------------------------------------- * PLL_N | 336 *----------------------------------------------------------------------------- * PLL_P | 2 *----------------------------------------------------------------------------- * PLL_Q | 7 *----------------------------------------------------------------------------- * PLLI2S_N | 426 *----------------------------------------------------------------------------- * PLLI2S_R | 4 *----------------------------------------------------------------------------- * I2S input clock(Hz) | 106500000 * | * To achieve the following I2S config: | * - Master clock output (MCKO): ON | * - Frame wide : 16bit | * - Audio sampling freq (KHz) : 32 | * - Error % : 0.0038 | * - Prescaler Odd factor (ODD): 1 | * - Linear prescaler (DIV) : 6 | *----------------------------------------------------------------------------- * VDD(V) | 3.3 *----------------------------------------------------------------------------- * Main regulator output voltage | Scale1 mode *----------------------------------------------------------------------------- * Flash Latency(WS) | 5 *----------------------------------------------------------------------------- * Prefetch Buffer | OFF *----------------------------------------------------------------------------- * Instruction cache | ON *----------------------------------------------------------------------------- * Data cache | ON *----------------------------------------------------------------------------- * Require 48MHz for USB OTG FS, | Disabled * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2> * * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx_system * @{ */ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ #include "stm32f4xx.h" /** * @} */ /** @addtogroup STM32F4xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Defines * @{ */ /************************* Miscellaneous Configuration ************************/ /*!< Uncomment the following line if you need to use external SRAM mounted on STM324xG_EVAL/STM324x7I_EVAL board as data memory */ /* #define DATA_IN_ExtSRAM */ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.