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The Intel® Atom™ Processor E3800 Product Family is the Intel Architecture (IA) SoC that integrates the next generation Intel® processor core, Graphics, Memory Controller, and I/O interfaces into a single system-on-chip solution.
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Document Number: 538136, Rev.4.2
Intel
®
Atom™ Processor E3800
Product Family
Datasheet
December 2016
Revision 4.2
Intel
®
Atom™ Processor E3800 Product Family
Datasheet December 2016
2 Document Number: 538136, Rev. 4.2
By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel
products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted
which includes subject matter disclosed herein.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the
absence or characteristics of any features or instructions marked “reserved” or “undefined.” Do not finalize a design with this
information.
The products described in this document may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained
by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm
Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied
and no license, express or implied, by estoppel or otherwise, to any of the reprinted source code is granted by this document.
[When the doc contains software source code for a special or limited purpose (such as informational purposes only), use the
conditionalized Software Disclaimer tag. Otherwise, use the generic software source code disclaimer from the Legal page and
include a copy of the software license or a hyperlink to its permanent location.]
This document contains information on products in the design phase of development.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,
not across different processor families. Go to: http://www.intel.com/products/processor_number/
Code Names are only for use by Intel to identify products, platforms, programs, services, etc. (“products”) in development by Intel
that have not been made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as
“commercial” names for products. Also, they are not intended to function as trademarks.
Intel, Intel Atom, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2016, Intel Corporation. All rights reserved
Intel
®
Atom™ Processor E3800 Product Family
December 2016 Datasheet
Document Number: 538136, Rev.4.2 3
Contents
1Introduction............................................................................................................ 31
1.1 Terminology ..................................................................................................... 33
1.2 Feature Overview .............................................................................................. 34
2Physical Interfaces.................................................................................................. 40
2.1 Pin States Through Reset ................................................................................... 42
2.2 System Memory Controller Interface Signals ......................................................... 43
2.3 PCI Express* 2.0 Interface Signals ...................................................................... 45
2.4 USB 2.0 Host (EHCI/xHCI) Interface Signals ......................................................... 45
2.5 USB 2.0 HSIC Interface Signals........................................................................... 46
2.6 USB 3.0 (xHCI) Host Interface Signals ................................................................. 46
2.7 USB 2.0 Device (ULPI) Interface Signals............................................................... 46
2.8 USB 3.0 Device Interface Signals......................................................................... 47
2.9 Serial ATA (SATA) 2.0 Interface Signals ............................................................... 48
2.10 Integrated Clock Interface Signals ....................................................................... 48
2.11 Display - Digital Display Interface (DDI) Signals .................................................... 49
2.12 Display – VGA Interface Signals .......................................................................... 50
2.13 MIPI Camera Serial Interface (CSI) and ISP Interface Signals.................................. 50
2.14 Intel
®
High Definition Audio Interface Signals ....................................................... 51
2.15 Low Power Engine (LPE) for Audio (I
2
S) Interface Signals ....................................... 51
2.16 Storage Control Cluster (eMMC, SDIO, SD) Interface Signals................................... 52
2.17 SIO – High Speed UART Interface Signals............................................................. 53
2.18 SIO – I
2
C Interface Signals................................................................................. 54
2.19 SIO – Serial Peripheral Interface (SPI) Signals ...................................................... 54
2.20 PCU – iLB – Real Time Clock (RTC) Interface Signals .............................................. 55
2.21 PCU – iLB – Low Pin Count (LPC) Bridge Interface Signals....................................... 55
2.22 PCU – Serial Peripheral Interface (SPI) Signals ...................................................... 56
2.23 PCU – System Management Bus (SMBus) Interface Signals..................................... 57
2.24 PCU – Power Management Controller (PMC) Interface Signals.................................. 57
2.25 JTAG and Debug Interface Signals ....................................................................... 58
2.26 Miscellaneous Signals......................................................................................... 58
2.27 GPIO Signals .................................................................................................... 59
2.28 Power And Ground Pins ...................................................................................... 63
2.29 Hardware Straps ............................................................................................... 65
2.30 Configurable IO: GPIO Muxing ............................................................................ 66
2.31 Reserved Pins ................................................................................................... 66
3 Register Access Methods ......................................................................................... 67
3.1 Fixed IO Register Access .................................................................................... 67
3.2 Fixed Memory Mapped Register Access................................................................. 67
3.3 IO Referenced Register Access ............................................................................ 67
3.4 Memory Referenced Register Access .................................................................... 68
3.5 PCI Configuration Register Access........................................................................ 68
3.6 Message Bus Register Access .............................................................................. 70
3.7 Register Field Access Types ................................................................................ 71
4 Mapping Address Spaces ......................................................................................... 73
4.1 Physical Address Space Mappings ........................................................................ 73
4.2 IO Address Space.............................................................................................. 79
Intel
®
Atom™ Processor E3800 Product Family
Datasheet December 2016
4 Document Number: 538136, Rev.4.2
4.3 PCI Configuration Space .....................................................................................81
5Integrated Clock......................................................................................................84
5.1 Features...........................................................................................................85
6 Power Management .................................................................................................88
6.1 Power Management Features...............................................................................88
6.2 Power Management States Supported...................................................................88
6.3 Processor Core Power Management ......................................................................93
6.4 Memory Controller Power Management .................................................................99
6.5 PCI Express* (PCIe*) Power Management...........................................................101
7 Power Up and Reset Sequence...............................................................................102
7.1 SoC System States ..........................................................................................102
7.2 Power Up Sequences ........................................................................................ 102
7.3 Power Down Sequences....................................................................................107
7.4 Reset Behavior ................................................................................................ 110
8 Thermal Management ............................................................................................113
8.1 CPU Thermal Management Registers .................................................................. 113
8.2 Thermal Sensors..............................................................................................113
8.3 SoC Programmable Trips ..................................................................................114
8.4 Platform Trips .................................................................................................115
8.5 Thermal Throttling Mechanisms .........................................................................115
8.6 Thermal Status................................................................................................115
9 Electrical Specifications .........................................................................................116
9.1 Thermal Specifications...................................................................................... 116
9.2 Storage Conditions...........................................................................................117
9.3 Voltage and Current Specifications .....................................................................118
9.4 Crystal Specifications ....................................................................................... 128
9.5 DC Specifications .............................................................................................129
9.6 AC Specifications ............................................................................................. 151
10 Ballout and Package Information...........................................................................211
10.1 SoC Attributes.................................................................................................211
10.2 Package Diagrams ...........................................................................................212
10.3 Ball Name and Function by Location ...................................................................213
10.4 Alphabetical Ball Name List ............................................................................... 261
11 Processor Core.......................................................................................................272
11.1 Features.........................................................................................................272
11.2 Platform Identification and CPUID ...................................................................... 275
11.3 References......................................................................................................276
12 System Memory Controller.....................................................................................277
12.1 Signal Descriptions .......................................................................................... 277
12.2 Features.........................................................................................................281
12.3 System Memory Controller (D-Unit) Message Registers .........................................285
13 SoC Transaction Router..........................................................................................320
13.1 Transaction Router A-Unit Message Registers ...................................................... 322
13.2 SoC Transaction Router PCI Config Access IO Registers......................................... 325
13.3 Transaction Router B-Unit Message Registers ...................................................... 327
13.4 Transaction Router C-Unit PCI Registers .............................................................342
Intel
®
Atom™ Processor E3800 Product Family
December 2016 Datasheet
Document Number: 538136, Rev.4.2 5
13.5 Transaction Router C-Unit Message Registers ...................................................... 349
13.6 Transaction Router P-Unit Message Registers ...................................................... 355
14 Graphics, Video and Display .................................................................................. 409
14.1 Features ........................................................................................................ 409
14.2 SoC Graphics Display ....................................................................................... 410
14.3 Display Pipes .................................................................................................. 411
14.4 Display Physical Interfaces ............................................................................... 411
14.5 References ..................................................................................................... 417
14.6 3D Graphics and Video..................................................................................... 417
14.7 Features ........................................................................................................ 418
14.8 VED (Video Encode/Decode) ............................................................................. 420
14.9 PCI Configuration Registers .............................................................................. 423
14.10 Memory Mapped Registers (1 of 2) .................................................................... 449
14.11 Memory Mapped Registers (2 of 2) .................................................................... 641
14.12 Memory Mapped Registers (Read Only) .............................................................1033
14.13 Memory Mapped Registers (Write Only).............................................................1039
15 MIPI-Camera Serial Interface (CSI) and ISP ........................................................1043
15.1 Signal Descriptions .........................................................................................1043
15.2 Features .......................................................................................................1045
15.3 Imaging Subsystem Integration .......................................................................1048
15.4 Functional Description.....................................................................................1050
15.5 MIPI-CSI-2 Receiver .......................................................................................1052
15.6 Register Map .................................................................................................1054
15.7 Image Signal Processor PCI Configuration Registers............................................1056
15.8 Image Signal Processor Memory Mapped IO Registers .........................................1082
16 Storage Control Cluster (eMMC, SDIO, SD Card) ...................................................1750
16.1 Signal Descriptions .........................................................................................1750
16.2 Features .......................................................................................................1752
16.3 References ....................................................................................................1754
16.4 Register Map .................................................................................................1755
16.5 SDIO for Wifi PCI Configuration Registers ..........................................................1757
16.6 SDIO for Wifi Memory Mapped IO Registers .......................................................1769
16.7 SD Card PCI Configuration Registers .................................................................1813
16.8 SD Card Memory Mapped IO Registers ..............................................................1825
16.9 eMMC 4.5 PCI Configuration Registers...............................................................1869
16.10 eMMC 4.5 Memory Mapped IO Registers............................................................1881
17 Serial ATA (SATA).................................................................................................1925
17.1 Signal Descriptions .........................................................................................1925
17.2 Features .......................................................................................................1926
17.3 References ....................................................................................................1928
17.4 Register Map .................................................................................................1929
17.5 SATA PCI Configuration Registers .....................................................................1930
17.6 SATA Legacy IO Registers ...............................................................................1959
17.7 SATA Index Pair IO Registers ...........................................................................1965
17.8 SATA AHCI Memory Mapped IO Registers ..........................................................1967
17.9 SATA Primary Read Command IO Registers .......................................................2004
17.10 SATA Primary Write Control IO Registers ...........................................................2009
17.11 SATA Primary Read Control IO Registers ...........................................................2010
17.12 SATA Primary Write Control IO Registers ...........................................................2011
17.13 SATA Secondary Read Command IO Registers....................................................2012
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