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数字设计：原理与实践

数字设计原理与实践答案

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145

EXERCISE SOLUTIONS

Sequential

Logic Design Practices

74x163

CLR

CLK

ENP

ENT

RCO

8.1 In the first three printings, change “

RAMBANK0

” to “

RAMBANK1

” in the third line of the exercise. The results are

the same. The new expression describes exactly the input combinations in which the 8 high-order bits of

ABUS

are 00000001

, the same as the original expression using don’t-cares.

8.2 The 16-series devices have or 2048 fuses (see Figure 10–2). The 20-series devices have or

2560 fuses.

8.3 There are fuses in the

AND

array (see Figure 10–4). Each of the eight macrocells has one fuse

to control the output polarity and one fuse to select registered vs. combinational configuration in the 16V8R, or

to assert the output-enable in the 16V8S. There are also two global fuses to select the overall configuration

(16V8C, 16V8R, or 16V8S). The total number of fuses is therefore .

A real 16V8 (depending on the manufacturer) has at least 64 additional fuses to disable individual product

terms, 64 user-programmable fuses that do nothing but store a user code, and a security fuse. (Once the security

fuse is programmed, the rest of the fuse pattern can no longer be read.)

8.5 The column below gives the answers in MHz.

Part numbers Suffix

PAL16L8, PAL16Rx, PAL20L8, PAL20Rx -5 5 4 – 4.5 0 117.7 117.7

PAL16L8, PAL16Rx, PAL20L8, PAL20Rx -7 7.5 6.5 – 7 0 74.1 74.1

PAL16L8, PAL16Rx, PAL20L8, PAL20Rx -10 10 8 – 10 0 55.6 55.6

GAL22V10 -25 25 15 13 15 0 33.3 35.7

64 32× 64 40×

64 32× 2048=

2048 16 2+ + 2066=

maxE

maxI

146 DIGITAL CIRCUITS

8.6 The column above gives the answers in MHz.

8.7

module Eight_Bit_Reg

title ’8-bit Edge-Triggered Register’

Z74X374 device ’P16V8R’;

" Input pins

CLK, !OE pin 1, 11;

D1, D2, D3, D4, D5, D6, D7, D8 pin 2, 3, 4, 5, 6, 7, 8, 9;

" Output pins

Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 pin 19, 18, 17, 16, 15, 14, 13, 12;

" Set definitions

D = [D1,D2,D3,D4,D5,D6,D7,D8];

Q = [Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8];

equations

Q := D;

end Eight_Bit_Reg

8.10 If

CLK

is 0, the output will be stable. If both are 1, the results are unpredictable, since they depend on

circuit timing. It is certain that the circuit’s output will be unstable as long as this condition is true.

8.11 The counter is modified to return to a count of 0 when count 9 is reached.

8.13 The counting direction is controlled by

: count up when

=1, count down when

=0. A load occurs

when the counter is in the terminal state, 1111 when counting up, 0000 when counting down. The MSB is com-

plemented during a load and the other bits are unchanged.

Let us assume that the counter is initially in one of the states 0000–0111. Then the counter counts down

(

=0). Upon reaching state 0000, it loads 1000 and subsequently counts up (

=1). Upon reaching state

1111, the counter loads 0111, and subsequently counts down, repeating the cycle.

module Z74x162

title '4-bit Decade Counter'

"Z74X162 device 'P16V8R';

" Input pins

CLK, !OE pin 1, 11;

A, B, C, D pin 2, 3, 4, 5;

!LD, !CLR, ENP, ENT pin 6, 7, 8, 9;

" Output pins

QA, QB, QC, QD pin 19, 18, 17, 16 istype 'reg';

RCO pin 15;

" Set definitions

INPUT = [ D, C, B, A ];

COUNT = [QD, QC, QB, QA ];

equations

COUNT.CLK = CLK;

COUNT := !CLR & ( LD & INPUT

# !LD & (ENT & ENP) & (COUNT < 9) & (COUNT + 1)

# !LD & (ENT & ENP) & (COUNT == 9) & 0

# !LD & !(ENT & ENP) & COUNT);

RCO = (COUNT == 9) & ENT;

end Z74x162

maxI

EXERCISE SOLUTIONS 147

If the counter is initially in one of the states 1000–1111, the same cyclic behavior is observed. The counting

sequence has a period of 16 and is, in decimal,

8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, 1, 0, 8, 9, ...

If only the three LSBs are observed, the sequence is

0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, ...

8.14 The only difference between a ’163 and a ’161 is that the

CLR_L

input of ’161 is asynchronous. Thus, the

counter will go from state 1010 to state 0000 immediately, before the next clock tick, and go from state 0000 to

state 0001 at the clock tick. Observing the state just before each clock tick, it is therefore a modulo-10 counter,

with the counting sequence 0, 1, ..., 9, 0, 1, ....

Note that this type of operation is not recommended, because the width of the

CLR_L

pulse is not well con-

trolled. That is, the

NAND

gate will negate the

CLR_L

pulse as soon as either one of its inputs goes to 0. If, say,

the counter’s

output clears quickly, and its

output clears slowly, it is possible for

CLR_L

to be asserted

long enough to clear

but not

, resulting in an unexpected next state of 1000, or possibly metastability of

the

output.

8.17 The path from the

counter output (

decoder input) to the

Y2_L

output has 10 ns more delay than the

and

(

and

) paths. Let us examine the possible

Y2_L

glitches in Figure 8–43 with this in mind:

3→4 (011→100) Because of the delay in the

path, this transition will actually look like 011→110→100.

The

Y6_L

output will have a 10-ns glitch, but

Y2_L

will not.

7→0 (111→000) Because of the delay in the

path, this transition will actually look like 111→010→000.

The

Y2_L

output will have a 10-ns glitch, but the others will not.

8.19 The delay calculation is different, depending on the starting state.

In the

INIT

state,

and

take 21 ns to propagate the

CLEAR

signal to the outputs. Then

requires 20 ns

setup time on its

inputs while

requires 20 ns setup time on its

RIN

input. This implies a minimum clock

period of 41 ns, assuming zero delay from the control unit.

In states

–

, the minimum clock period depends on the delay of the combinational logic in the control unit

that asserts

SELSUM

when

MPY0

is asserted. However, the most obvious way to do this is to connect

MPY0

directly to

SELSUM

, creating a delay of 0 ns. This assumption is made below. Also, it is assumed that

MPY0

1 to find the worst case. The figure on the next page shows the worst-case path, in heavy lines, to be 106 ns.

Since we would like to use the same clock for all states, the minimum clock period is 106 ns.

148 DIGITAL CIRCUITS

U6 Q

outputs

valid

U2, U3

outputs

valid

U4 C4

output

valid

U5 C4

output

valid

U5 S

outputs

valid

U7 & U8

outputs

valid

U4 S

outputs

valid

24ns

16ns

21ns

16ns

24ns

27ns

39ns

14ns

24ns

U9 gate

output

valid

27ns

U6 D

inputs

set up

20ns

U3 RIN

input set

20ns

Ready

for next

clock

Clock

edge

EXERCISE SOLUTIONS 149

8.20 The synchronizer fails if

META

has not settled by the beginning of the setup-time window for

FF2

, which is

5 ns before the clock edge. Since the clock period is 40 ns, the available metastability resolution time is 35 ns.

The MTBF formula is

Substituting the proper values of and for the ’F74, and of and for the problem, we calculate

8.22 Refer to the sample data sheet on page 169 of the text: “Not more than one output should be shorted at a time;

duration of short-circuit should not exceed one second.” In the switch debounce circuit, the short lasts only for

a few tens of nanoseconds, so it’s OK.

8.23 CMOS outputs can “latch up” under certain conditions. According to the Motorola High-Speed CMOS Logic

Data book (1988 edition, pp. 4–10), a 74HCT output can latch up if a voltage outside the range

is forced on the output by an external source. In a switch debounce circuit using

74HCT04s, the switch connection to ground is an external source, but the voltage (0 V) is within the acceptable

range and should not be a problem.

Another potential problem is excessive short-circuit current, but again the data book indicates that shorting the

output briefly is not a problem, as long as “the maximum package power dissipation is not violated” (i.e., the

short is not maintained for a long time).

Similar considerations apply to 74AC and 74ACT devices, but in the balance, such devices are not recom-

mended in the switch-debounce application, as we’ll explain. On one hand, typical 74AC/74ACT devices are

even less susceptible to latch-up than 74HCT devices. (For example, see the Motorola FACT Data book, 1988

edition, pp. 2–9.) On the other hand, 74AC/74ACT’s high performance may create noise problems for other

devices in a system. In particular, when the 74AC/74ACT

HIGH

output is shorted to ground, it may momen-

tarily drag the local 5 V power-supply rail down with it, especially if the decoupling capacitors are small, far

away, or missing. This will in turn cause incorrect operation of the other, nearby logic devices.

8.25 TTL inputs require significant current, especially in the

LOW

state. The bus holder cannot supply enough

current unless the series resistor is made much smaller, which then creates a significant load on the bus.

MTBF t

()

τ⁄()exp

f⋅ a⋅

------------------------=

τ T

MTBF 35ns()

35 0.4⁄()exp

2.0 10

4–

⋅⋅⋅

-------------------------------------------

210

s⋅≈=

0.5– V

out

0.5V+≤≤

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ergyioreya

2012-12-24

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