10/28/2011 1 Version 0.8
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
ÁЉꗬꗬ
NT35510
One-chip Driver IC with internal GRAM
for 16.7M colors 480RGB x 864 a-Si TFT LCD
with CPU / RGB / MIPI / MDDI Interface
or without internal CGRAM
for 16.7M colors 480RGB x 1024 a-Si TFT LCD
with RGB Interface
V0.8
Preliminary
PRELIMINARY NT35510
10/28/2011 Version 0.8
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
2
REVISION HISTORY................................................................................................................................................8
1 DESCRIPTION ....................................................................................................................................................12
1.1
PURPOSE OF THIS DOCUMENT .............................................................................................................................12
1.2
GENERAL DESCRIPTION ......................................................................................................................................12
2 FEATURES .........................................................................................................................................................13
3 BLOCK DIAGRAM..............................................................................................................................................15
4 PIN DESCRIPTION .............................................................................................................................................16
4.1
POWER SUPPLY PINS..........................................................................................................................................16
4.2 80-SYSTEM INTERFACE PINS...............................................................................................................................17
4.3
SPI /I2C INTERFACE PINS ...................................................................................................................................17
4.4 RGB INTERFACE PINS ........................................................................................................................................18
4.5
MIPI/MDDI INTERFACE PINS...............................................................................................................................19
4.6 INTERFACE LOGIC PINS.......................................................................................................................................20
4.7
DRIVER OUTPUT PINS .........................................................................................................................................22
4.8 DC/DC CONVERTER PINS ...................................................................................................................................23
4.9 LABC AND CABC CONTROL PINS ...............................................................................................................25
4.10 TEST PINS .....................................................................................................................................................26
5 FUNCTIONAL DESCRIPTION............................................................................................................................27
5.1
MPU INTERFACE.................................................................................................................................................27
5.1.1 Interface Type Selection .......................................................................................................................................27
5.1.2 80-series MPU Interface........................................................................................................................................28
5.1.3 Serial Interface.......................................................................................................................................................46
5.2 I2C INTERFACE...................................................................................................................................................55
5.2.1 Slave Address of I2C.............................................................................................................................................56
5.2.2 Register Write Sequence of I2C Interface ...........................................................................................................56
5.2.3 RAM Data Write Sequence of I2C Interface.........................................................................................................56
5.2.4 Register Read Sequence of I2C Interface ...........................................................................................................60
5.2.5 RAM Data Read Sequence of I2C Interface.........................................................................................................60
5.3 MIPI INTERFACE .................................................................................................................................................64
5.3.1 Display Module Pin Configuration for DSI ..........................................................................................................65
5.3.2 Display Serial Interface (DSI) ...............................................................................................................................66
5.3.3 Memory Write/Read Format................................................................................................................................152
5.3.4 System Power-Up and Initialization...................................................................................................................159
5.4
MDDI INTERFACE .............................................................................................................................................160
5.4.1 MDDI Link Protocol by The NT35510.................................................................................................................161
PRELIMINARY NT35510
10/28/2011 Version 0.8
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
3
5.4.2 MDDI Link Packet Descriptions by the NT35510 ..............................................................................................162
5.4.3 Writing Video Data to Memory Sequence..........................................................................................................172
5.4.4 Writing Register Sequence.................................................................................................................................172
5.4.5 Reading Video Data from Memory Sequence ...................................................................................................173
5.4.6 Reading Register Sequence...............................................................................................................................173
5.4.7 Hibernation Setting.............................................................................................................................................174
5.4.8 MDDI Deep Standby Mode Setting.....................................................................................................................175
5.5 INTERFACE PAUSE ............................................................................................................................................177
5.6 DATA TRANSFER BREAK AND RECOVERY ..........................................................................................................178
5.7
DISPLAY MODULE DATA TRANSFER MODES.......................................................................................................180
5.8 RGB INTERFACE...............................................................................................................................................181
5.8.1 General Description ............................................................................................................................................181
5.8.2 RGB Interface Timing Chart ...............................................................................................................................182
5.8.3 RGB Interface Mode Set .....................................................................................................................................183
5.8.4 RGB Interface Bus Width Set.............................................................................................................................187
5.9 FRAME MEMORY...............................................................................................................................................191
5.9.1 Configuration.......................................................................................................................................................191
5.9.2 Address Counter .................................................................................................................................................192
5.9.3 Interface to Memory Write Direction..................................................................................................................193
5.9.4 Frame Memory to Display Address Mapping....................................................................................................194
5.10 TEARING EFFECT INFORMATION.......................................................................................................................195
5.10.1 Tearing Effect Output Line ...............................................................................................................................195
5.10.2 Tearing Effect Bus Trigger................................................................................................................................200
5.11
CHECKSUM.....................................................................................................................................................212
5.12
POWER ON/OFF SEQUENCE ............................................................................................................................214
5.12.1 Case 1 – RESX line is held High or Unstable by Host at Power On..............................................................215
5.12.2 Case 2 – RESX line is held Low by host at Power On....................................................................................216
5.12.3 Uncontrolled Power Off ....................................................................................................................................216
5.13 POWER LEVEL MODES ....................................................................................................................................217
5.13.1 Definition............................................................................................................................................................217
5.13.2 Power Level Mode Flow Chart..........................................................................................................................218
5.14
RESET FUNCTION ............................................................................................................................................220
5.14.1 Register Default Value ......................................................................................................................................220
5.14.2 Output or Bi-directional (I/O) Pins ...................................................................................................................222
5.14.3 Input Pins...........................................................................................................................................................222
PRELIMINARY NT35510
10/28/2011 Version 0.8
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
4
5.15 SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE ......................................223
5.15.1 Register loading Detection...............................................................................................................................223
5.15.2 Functionality Detection.....................................................................................................................................224
5.15.3 Chip Attachment Detection ..............................................................................................................................225
5.16
DISPLAY PANEL COLOR CHARACTERISTICS.....................................................................................................226
5.17
GAMMA FUNCTION ..........................................................................................................................................227
5.18 BASIC DISPLAY MODE.....................................................................................................................................228
5.19
INSTRUCTION SETTING SEQUENCE...................................................................................................................229
5.19.1 Sleep In/Out Sequence .....................................................................................................................................229
5.19.2 Deep Standby Mode Enter/Exit Sequence.......................................................................................................230
5.20
INSTRUCTION SETUP FLOW .............................................................................................................................231
5.20.1 Initializing with the Built-in Power Supply Circuits........................................................................................231
5.20.2 Power OFF Sequence .......................................................................................................................................232
5.21 MTP WRITE SEQUENCE ..................................................................................................................................233
5.22 DYNAMIC BACKLIGHT CONTROL FUNCTION......................................................................................................234
5.22.1 PWM Control Architecture................................................................................................................................236
5.22.2 Dimming Function for LABC and Manual Brightness Control......................................................................241
5.22.3 Dimming Function for CABC and Force PWM Function................................................................................244
5.22.4 PWM Signal Setting for CABC and LABC .......................................................................................................245
5.22.5 Content Adaptive Brightness Control (CABC)................................................................................................247
5.22.6 Ambient Light Sensor and Automatic Brightness Control (LABC)...............................................................248
5.23
COLUMN, 1-DOT, 2-DOT, 3-DOT AND 4-DOT INVERSION (VCOM DC DRIVE).....................................................255
6 COMMAND DESCRIPTIONS ...........................................................................................................................256
6.1
USER COMMAND SET........................................................................................................................................256
NOP (0000h)..................................................................................................................................................................260
SWRESET: Software Reset (0100h) ............................................................................................................................261
RDDID: Read Display ID (0400h~0402h).....................................................................................................................262
RDNUMED: Read Number of Errors on DSI (0500h)..................................................................................................263
RDDPM: Read Display Power Mode (0A00h) .............................................................................................................264
RDDMADCTL: Read Display MADCTL (0B00h)..........................................................................................................265
RDDCOLMOD: Read Display Pixel Format (0C00h) ..................................................................................................266
RDDIM: Read Display Image Mode (0D00h) ...............................................................................................................267
RDDSM: Read Display Signal Mode (0E00h) .............................................................................................................268
RDDSDR: Read Display Self-Diagnostic Result (0F00h)...........................................................................................269
SLPIN: Sleep In (1000h) ...............................................................................................................................................270
PRELIMINARY NT35510
10/28/2011 Version 0.8
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
5
SLPOUT: Sleep Out (1100h).........................................................................................................................................272
PTLON: Partial Display Mode On (1200h) ..................................................................................................................274
NORON: Normal Display Mode On (1300h)................................................................................................................275
INVOFF: Display Inversion Off (2000h).......................................................................................................................276
INVON: Display Inversion On (2100h).........................................................................................................................277
ALLPOFF: All Pixel Off (2200h) ...................................................................................................................................278
ALLPON: All Pixel On (2300h).....................................................................................................................................280
GAMSET: Gamma Set (2600h).....................................................................................................................................282
DISPOFF: Display Off (2800h) .....................................................................................................................................283
DISPON: Display On (2900h) .......................................................................................................................................284
CASET: Column Address Set (2A00h~2A03h) ...........................................................................................................285
RASET: Row Address Set (2B00h~2B03h).................................................................................................................287
RAMWR: Memory Write (2C00h) .................................................................................................................................289
RAMRD: Memory Read (2E00h) ..................................................................................................................................290
PTLAR: Partial Area (3000h~3003h)............................................................................................................................291
TEOFF: Tearing Effect Line OFF (3400h)....................................................................................................................294
TEON: Tearing Effect Line ON (3500h) .......................................................................................................................295
MADCTL: Memory Data Access Control (3600h).......................................................................................................296
IDMOFF: Idle Mode Off (3800h)...................................................................................................................................299
IDMON: Idle Mode On (3900h).....................................................................................................................................300
COLMOD: Interface Pixel Format (3A00h)..................................................................................................................302
RAMWRC: Memory Write Continue (3C00h)..............................................................................................................303
RAMRDC: Memory Read Continue (3E00h) ...............................................................................................................304
STESL: Set Tearing Effect Scan Line (4400h~4401h)................................................................................................305
GSL: Get Scan Line (4500h~4501h)............................................................................................................................307
DPCKRGB: Display Clock in RGB Interface (4A00h) ................................................................................................308
DSTBON: Deep Standby Mode On (4F00h) ................................................................................................................309
WRPFD: Write Profile Value for Display (5000h~500Fh)...........................................................................................310
WRDISBV: Write Display Brightness (5100h) ............................................................................................................311
RDDISBV: Read Display Brightness (5200h) .............................................................................................................312
WRCTRLD: Write CTRL Display (5300h) ....................................................................................................................313
RDCTRLD: Read CTRL Display Value (5400h)...........................................................................................................315
WRCABC: Write Content Adaptive Brightness Control (5500h) ..............................................................................317
RDCABC: Read Content Adaptive Brightness Control (5600h) ...............................................................................318
WRHYSTE: Write Hysteresis (5700h~573Fh) .............................................................................................................319
