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### CYPRESS USB3.0 UVC设计规范详解 #### 引言 CYPRESS USB3.0 UVC设计规范是一份重要的文档，它详细介绍了如何利用Cypress EZ-USB® FX3™ 设备控制器来实现与USB视频类（UVC）兼容的图像传感器接口设计。这份规范尤其适用于那些希望在不依赖FPGA的情况下实现USB视频流传输的开发者们。通过本文档，我们将深入了解CYPRESS USB3.0 UVC设计规范中的关键知识点。 #### 设计GPIF II接口 GPIF II是Cypress EZ-USB® FX3™ 设备的一个通用可编程接口，它可以轻松连接到各种设备。为了使FX3能够与图像传感器通信并符合USB视频类标准，需要正确设计GPIF II接口。 - **图像传感器接口**：首先需要定义图像传感器与FX3之间的接口规范。这包括确定信号线、时序和数据格式等。 - **GPIF II描述符需求**：根据图像传感器的具体需求，设计出满足其传输特性的GPIF II描述符。 - **引脚映射**：将图像传感器接口的信号线与FX3的GPIF II接口进行匹配。 - **GPIF II DMA能力**：确保GPIF II支持所需的DMA模式，以便高效地传输图像数据。 - **状态机设计**：定义用于控制图像数据读取和传输的状态机。 #### 图像传感器波形、数据路径与状态机之间的关联为了确保图像数据能够准确无误地从传感器传送到FX3，并最终通过USB输出，必须仔细设计这些组件之间的交互关系。 - **图像传感器波形**：理解传感器产生的数据信号特性。 - **数据路径**：定义图像数据从传感器到达FX3的路径。 - **状态机**：创建控制数据传输流程的状态机逻辑。 #### 集成GPIF II描述符将GPIF II描述符集成到FX3中是一项关键步骤，这涉及到软件配置和硬件设置。 - **配置描述符**：确保GPIF II描述符与FX3的硬件和软件环境兼容。 - **USB视频类要求**：满足USB视频类标准对设备的要求。 #### 创建DMA通道以传输数据为了实现高效的图像数据传输，需要在FX3内部设置适当的DMA通道。 - **DMA配置**：定义DMA通道的参数，如源地址、目标地址、数据长度等。 - **DMA触发**：确定何时启动DMA传输以及传输的条件。 #### 固件应用程序执行路径固件应用程序控制着整个视频流传输的过程，包括初始化、枚举、开始流传输、处理缓冲区以及清理工作。 - **初始化**：设置FX3及其外围设备的初始状态。 - **枚举**：通过USB协议完成设备的识别过程。 - **开始流传输**：启动图像数据的传输过程。 - **处理缓冲区**：管理传输过程中使用的缓冲区。 - **清理**：结束传输后进行必要的资源释放操作。 - **终止流传输**：停止图像数据的传输，并恢复设备至初始状态。 #### 固件示例项目细节文档还提供了一个具体的固件示例项目，用于演示上述概念的实际应用。 - **项目配置**：设置项目的环境和工具链。 - **代码结构**：了解项目中各个模块的作用和组织方式。 - **测试与验证**：验证项目是否按预期工作。 #### 总结本设计规范提供了全面的指导，帮助开发者实现基于Cypress EZ-USB® FX3™ 的USB视频流传输功能。通过遵循这些指南，可以避免复杂的FPGA设计，并简化整个开发流程。 #### 作者简介 Karnik Shah 是该文档的作者，拥有丰富的USB技术和图像传感器接口经验。如果在阅读或应用该应用笔记时遇到问题，可以通过电子邮件联系作者寻求帮助。 #### 附录A：使用GPIF II Designer设计文档还介绍了如何使用GPIF II Designer工具来辅助设计GPIF II接口，包括创建项目、选择接口定义、绘制状态机以及编辑接口详细信息等步骤。通过以上内容的详细解析，我们可以看到CYPRESS USB3.0 UVC设计规范不仅为开发者提供了一套完整的方案来实现USB视频流传输功能，而且还提供了一系列实用的工具和示例项目来加速开发进程。这对于希望快速实现USB视频功能而无需深入FPGA设计的项目来说，是非常有价值的资源。

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www.cypress.com Document No. 001-75779 Rev. *A 1

AN75779

Interfacing an Image Sensor to EZ-USB

FX3™ in a USB video class (UVC)

Framework

Author: Karnik Shah

Associated Project: Yes

Software Version: FX3 SDK1.1

Related Application Notes: None

If you have a question, or need help with this application note, contact the author at

SHAH@cypress.com.

Cypress’s EZ-USB® FX3™ is a USB 3.0 peripheral controller with a general programmable interface, called GPIF II,

which can connect easily to a range of devices. This application note describes a video streaming application compatible

with USB video class (UVC) where FX3 streams images from an image sensor to a USB host.

Table of Contents

Introduction ....................................................................... 1

Designing the GPIF II interface ......................................... 2

Image Sensor Interface ................................................ 2

Requirements for GPIF II Descriptor .................................. 3

Pin Mapping of Image Sensor Interface ....................... 3

GPIF II DMA Capabilities.............................................. 4

GPIF II State Machine Design ...................................... 7

Correlation between Image Sensor Waveforms, Data

Path and State Machine ............................................... 8

Integration of the GPIF II Descriptor ............................. 9

USB Video Class Requirements ....................................... 9

Creating a DMA channel to stream data from GPIF II to

USB ................................................................................. 10

Execution path of the firmware application ...................... 10

Application Threads .................................................... 10

Enumeration ............................................................... 11

Starting the streaming ................................................ 11

Handling the buffers during streaming ........................ 11

Clean Up .................................................................... 11

Aborting the streaming ............................................... 12

Firmware Example Project Details .................................. 12

Summary ......................................................................... 13

About the Author ............................................................. 13

Appendix A ...................................................................... 14

Designing with the GPIF II Designer ............................... 14

Creating the Project .................................................... 14

Choosing the Interface Definition ............................... 14

Drawing the State Machine on the Canvas ................ 17

Basic Drawing Actions on the Canvas ............................. 17

Drawing Image Sensor Interface State Machine .............. 20

Editing the GPIF II interface details ................................. 25

Document History ............................................................ 26

Introduction

EZ-USB® FX3™ is the USB 3.0 peripheral controller that

enables developers to add USB 3.0 device functionality to

any system. FX3 has a fully configurable General

Programmable Interface (GPIF™ II), which can interface

with virtually any processor, ASIC, image sensor or FPGA.

UVC is a USB standard class that allows a video

streaming device to be connected to a USB host to stream

video like a webcam using standard UVC driver. This

application note discusses how to design an application,

which is compatible with UVC, by interfacing FX3 and an

image sensor with an interface that has the following

signals: frame valid, line valid, pixel clock, and 8bit to 32bit

parallel data bus.

This application has been designed for an image sensor

with an 8-bit parallel data interface, 16bits per pixel, YUY2

color space, 1280 x 720 pixels resolution, 30 frames per

second, active high frame/line valid signals and positive

clock edge polarity. With some minor customizations, a

variety of sensors with a similar interface can also be

interfaced. Editing the GPIF II interface details section in

Appendix A describes how to change the data bus width

as an example of customization.

This application discusses the flow of data from the image

sensor to the internal buffers and then to the USB3 host,

Interfacing an Image Sensor to EZ-USB® FX3™ in a USB video class (UVC) Framework

www.cypress.com Document No. 001-75779 Rev. *A 2

while explaining the parts of design required to implement

this data flow. These parts include designing an interface

waveform for the GPIF II, creating a USB descriptor to

enumerate FX3 as a UVC device, and connecting the

GPIF II to the USB via a DMA channel for streaming. An

overview of the whole system is shown in the system

block diagram Figure 1. A host application like AMCap

talks through the UVC driver to configure the image

sensor over video control interface and receive video data

over the video streaming interface. FX3 firmware

translates the video control settings to the Image Sensor

over GPIO or I2C interface. FX3 DMA channel streams

data from the Image Sensor to internal buffers where UVC

header is added to the image data. This video data is then

sent to the video streaming endpoint.

Designing the GPIF II interface

To design an interface waveform, an understanding of the

interface requirements and DMA capabilities of FX3 is

required. Additionally, the class specific requirements of

USB video class (UVC) also need to be addressed to

make the application compatible with UVC standards.

Image Sensor Interface

A standard image sensor interface looks like the interface

between the image sensor and FX3 shown in Figure 1.

Usually, the image sensor requires a reset signal from the

FX3 controller. This can be handled by using an FX3

GPIO. Image sensors typically use an I

C connection to

allow a controller to configure the image sensor

parameters. The I

C block of FX3 can act as an I

master to configure the image sensor with the correct

parameters. The various signals that are associated with

transferring an image are as follows: (these unidirectional

signals are from image sensor to FX3)

1. FV - Frame Valid (indicates start and stop of a frame)

2. LV - Line Valid (indicates start and stop of a line)

3. PCLK – Pixel clock (clock for the synchronous

interface)

4. Data – 8 to 32 bit data lines for image data

Figure 1. System block diagram

Image Sensor

PCLK

Frame Valid

Line Valid

Data bus

Reset#

I2C control

Video Data

Video Control

USB Host

Application

(AMCap)

UVC

Driver

USB

Host

Controller

GPIO

GPIF

I2C

Master

USB3

FX3

DMA

Channel

USB

Bulk

IN EP

USB

EP0

Firmware

Video

Data

Figure 2 shows the timing diagram of the FV, LV, PCLK

and Data signals. The FV signal is asserted to indicate the

start of a frame. Then, the image data is transferred line

by line. The LV signal is asserted during each line transfer

when the data is driven by the image sensor. This data

can be 8bit to 32bit simultaneous transfer from the image

sensor.

Note This parallel data bus width is defined by the data

width as defined in the image sensor datasheet. Do not

confuse the data bus width with the bit depth/resolution of

the image sensor.

FX3 GPIF II bus can be configured only in 8, 16 or 32bit

data interfaces. Hence, the data bus width from FX3

should be set such that it is larger than or equal to the

image sensor data width. This size will be the interface

width over GPIF II. If the interface width is larger than the

image sensor data width, the additional padded bits

transferred should be discarded by the end application –

usually the software running on host PC. For example, if

the image sensor sends out 12bits in parallel, the interface

width should be set to 16bits and the unconnected 4bits

will behave as padding. The time between each line is

called the horizontal blanking. During horizontal blanking

no data is transferred and the LV signal is de-asserted.

Once all the lines are transferred from the image sensor,

the FV signal is de-asserted, and it remains de-asserted

for the time equivalent to the vertical blanking. A slave

state machine for this interface can be implemented using

the GPIF II to receive the image data from the image

sensor.

Interfacing an Image Sensor to EZ-USB® FX3™ in a USB video class (UVC) Framework

www.cypress.com Document No. 001-75779 Rev. *A 3

Requirements for GPIF II Descriptor

The previous section described a typical image sensor

interface. This section describes the design requirements,

which can be derived from the image sensor interface, for

the GPIF II state machine. Looking at the image sensor

interface timing diagram we can infer that:

- For image resolution C x R, where C is the number of

columns and R is the number of rows of pixels, and P is

the bytes per pixel (including the padding), an image

sensor continuously sends CxP bytes of image data; R

times with short pauses. So once a line starts, GPIF II

design should be able to move CxP bytes without a break

as there is no flow control on the image sensor interface.

- At the end of the frame, a signal must be generated from

GPIF II to the FX3 CPU so that the CPU indicates to the

host that the current frame data transfer is complete.

- FX3 can only operate in 8bit, 16bit or 32bit modes.

Hence, the data bus width for the GPIF II must be set such

that it is greater or equal to the parallel data coming out of

the image sensor.

An example GPIFII design for an image sensor has been

created using the GPIFII Designer tool and is attached

with this application note for reference. Steps to build it are

explained in detail in the “Designing with the GPIF II

designer” section (Appendix A).

The following section shows the pin mapping used in the

GPIFII implementation of the image sensor interface in

this application note.

Figure 2. Image Sensor Interface Timing Diagram

PCLK

DATA

Zoomed in

Line 1

Line 2

Line RLine R-1

D2 Dc

Horizontal Blanking

Vertical Blanking

Active Frame

Active Line

Pin Mapping of Image Sensor Interface

The pin mapping used in the GPIFII implementation of the parallel image sensor interface in this application note is shown in

Table 1 . Also shown are the GPIO pins and other serial interfaces (UART/SPI/I2S) available when you use the GPIF II

design available with this application note.

Table 1. Pin Mapping for Parallel Image Sensor Interface Descriptor

EZ-USB FX3 Pin

Synchronous Parallel Image Sensor

Interface with 16-bit Data Bus

Synchronous Parallel Image Sensor

Interface with 8-bit Data Bus

GPIO[28] LV LV

GPIO[29] FV FV

GPIO[0:7] DQ[0:7] DQ[0:7]

GPIO[8:15] DQ[8:15] Unused

GPIO[16] PCLK PCLK

GPIO[17:27] Available as GPIOs Available as GPIOs

Interfacing an Image Sensor to EZ-USB® FX3™ in a USB video class (UVC) Framework

www.cypress.com Document No. 001-75779 Rev. *A 4

Note For the complete pin mapping of EZ-USB FX3, please refer to the datasheet “EZ-USB FX3 SuperSpeed USB Controller.”

The following section explains the DMA configuration used

to achieve video streaming from FX3’s GPIFII to the USB

interface.

GPIF II DMA Capabilities

The GPIF II block, as a part of P (processor port) block, is

capable of running up to 100MHz with 32 bits of data

(400MBps). To transfer the data to internal buffers, GPIF II

uses threads connected to DMA producer sockets of the P

block. The sockets point to a DMA descriptor that sets

DMA buffer size, count and chaining sequence. The GPIF

II has four threads, and these four threads can be

associated with any four sockets of the 32 P block

sockets. Default settings are used for this application. The

default threads are associated with the sockets of the

same number. As shown in Figure 3, GPIF II has 4

threads through which it can transfer data. The switching

between these threads is accomplished by in-state thread

switching as explained in the “GPIF II State Machine

Design” section.

Figure 3. Default settings for GPIF II threads and P

block sockets

P Block

GPIF II

Socket 0

Thread 0

Thread 1

Thread 2

Thread 3

Socket 1

Socket 2

Socket 3

External

Data Bus

Switching

The DMA data transfer mechanism is shown in Figure 4.

The example is of a DMA channel where there is a single

producer socket (consumer side not shown) and three

buffers, of length L, chained in a linear circular loop. The

figure shows the internal memory of FX3. The left column

in the diagram shows the memory offset and the right

column shows what is stored in that memory location. The

red arrows (data path) indicate how the buffers will be

accessed by the socket. The blue arrows (connecting the

DMA descriptor chain to the socket) show how the socket

loads the descriptors from memory. The following

GPIO[33:45] Available as GPIOs Available as GPIOs

GPIO[46] GPIO/UART_RTS GPIO/UART_RTS

GPIO[47] GPIO/UART_CTS GPIO/UART_CTS

GPIO[48] GPIO/UART_TX GPIO/UART_TX

GPIO[49] GPIO/UART_RX GPIO/UART_RX

GPIO[50] GPIO/I2S_CLK GPIO/I2S_CLK

GPIO[51] GPIO/I2S_SD GPIO/I2S_SD

GPIO[52] GPIO/I2S_WS GPIO/I2S_WS

GPIO[53] GPIO/SPI_SCK /UART_RTS GPIO/SPI_SCK /UART_RTS

GPIO[54] GPIO/SPI_SSN/UART_CTS GPIO/SPI_SSN/UART_CTS

GPIO[55] GPIO/SPI_MISO/UART_TX GPIO/SPI_MISO/UART_TX

GPIO[56] GPIO/SPI_MOSI/UART_RX GPIO/SPI_MOSI/UART_RX

GPIO[57] GPIO/I2S_MCLK GPIO/I2S_MCLK

Interfacing an Image Sensor to EZ-USB® FX3™ in a USB video class (UVC) Framework

www.cypress.com Document No. 001-75779 Rev. *A 5

execution steps show the process or mechanism of data

moving from a socket to the internal buffers. The steps are

also marked in Figure 4 for reference.

Figure 4. Example to Explain DMA Data Transfer

Operation

DMA Descriptor 1

Buffer Address: A1 – Size L

Next DMA Descriptor: 2

DMA Descriptor 2

Buffer Address: A2 – Size L

Next DMA Descriptor: 3

DMA Descriptor 3

Buffer Address: A3 – Size L

Next DMA Descriptor: 1

DMA Buffer 1

A1+L

A2+L

DMA Buffer 2

DMA Buffer 3

A3+L

Socket

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Step 1: Load DMA descriptor 1 from the memory into the

socket. Get the buffer location (A1), buffer size (L) and

next descriptor (DMA descriptor 2) information. Go to step

Step 2: Transfer data to the buffer location starting at A1.

After transferring buffer size L amount of data, go to step

Step 3: Load DMA descriptor 2 as pointed to by the

current DMA descriptor 1. Get the buffer location (A2),

buffer size (L) and next descriptor (DMA descriptor 3)

information. Go to step 4.

Step 4: Transfer data to the buffer location starting at A2.

After transferring buffer size L amount of data, go to step

Step 5: Load DMA descriptor 3 as pointed to by the

current DMA descriptor 2. Get the buffer location (A3),

buffer size (L) and next descriptor (DMA descriptor 1)

information. Go to step 6.

Step 6: Transfer data to the buffer location starting at A3.

After transferring buffer size L amount of data, go to step

Notice that in this execution path, the socket is not

continuously transferring data. The socket pauses to get

configuration in between two buffers. There is a non zero

(typically 1us) delay when the socket switches buffers. For

only one socket implementation, the first requirement

from the requirement section can fail at buffer boundaries

if the buffers are not a multiple of line length.

One obvious solution is to use buffer sizes equal to a

multiple of the line size. Under such implementation, if the

resolution of the image changes, the buffer size needs to

be changed. Setting buffer size equal to line size will not

give maximum throughput either. USB3 allows a maximum

of 16 bursts of 1024 bytes over bulk endpoint. This feature

should be utilized for maximum throughput. To enable

USB burst of 16KB, the USB DMA buffer size (consumer

side) should be set to 16KB and so the P block DMA

buffer size (producer side) will be similar – explained in

USB video class requirements section. An alternate

method can be implemented where two sockets are used

from GPIF II side to write data in an interleaved fashion.

Since switching of sockets for GPIF II has no time latency,

the sockets can be switched when the buffer associated

with the active socket is full i.e. socket switching at the

exact buffer boundary as compared to line boundary. The

data transfer using dual sockets is described in Figure 5

with the execution steps labeled. Socket0 and Socket1

access to DMA buffers is differentiated with red and green

colored arrows (data paths for individual sockets/threads)

respectively. The ‘a’ and ‘b’ parts of each step occur

simultaneously. This parallel operation of the hardware

helps mask the buffer switching time and allows GPIF II to

stream data continuously into internal memory.

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xiao19890501

2014-08-06

官网上有的啊！！！！
register-success

2013-10-18

这个官网上都有！先看看吧！
juster000

2015-10-28

很一般，官网上有

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