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### 51单片机（AT89C51）知识点详解 #### 一、51单片机简介 51单片机是基于8位微处理器架构的一种嵌入式系统，广泛应用于各种电子产品的控制核心。其中，AT89C51作为51系列中的一个经典型号，因其低功耗、高性能以及丰富的内部资源而被广泛应用。 #### 二、AT89C51主要特点 1. **与MCS-51兼容**：AT89C51采用与MCS-51相同的标准指令集和引脚排列方式，方便开发者进行移植。 2. **4KB Flash内存**：内置可编程且可擦写的只读存储器（PEROM），支持1,000次写/擦周期，可以在系统内重新编程或通过非易失性存储器编程器进行编程。 3. **静态工作模式**：支持从0Hz到24MHz的工作频率范围，能够满足不同应用需求下的时钟速度要求。 4. **程序内存锁**：提供三级程序内存保护功能，增强系统的安全性。 5. **128×8位内部RAM**：拥有128个字节的片上数据存储空间，用于存放运行时的数据和中间结果。 6. **32个可编程I/O口**：具备丰富的输入/输出端口资源，支持各种外设连接。 7. **双16位定时器/计数器**：集成两个16位的定时器/计数器，可以用于定时控制或对外部脉冲进行计数。 8. **六个中断源**：包括外部中断、定时器溢出中断、串行口中断等，增强了系统的实时处理能力。 9. **可编程串行通信接口**：支持异步全双工串行通信，适用于远程数据传输。 10. **低功耗模式**：支持空闲和掉电两种低功耗模式，适用于电池供电的应用场合，有效延长电池寿命。 #### 三、AT89C51管脚配置 AT89C51采用不同的封装形式，常见的有PDIP、PQFP/TQFP、PLCC等。 - **PDIP封装**： - P1.0至P1.7：通用I/O端口； - RST：复位引脚； - RXD/P3.0、TXD/P3.1：串行通信端口； - INT0/P3.2、INT1/P3.3：外部中断输入； - T0/P3.4、T1/P3.5：定时器/计数器输入； - WR/P3.6、RD/P3.7：外部数据存储器控制信号； - XTAL1、XTAL2：晶体振荡电路连接点； - GND：电源地； - VCC：电源正极； - P0.0至P0.7：带地址/数据线的通用I/O端口； - EA/VPP：访问片内/片外程序存储器的选择； - ALE/PROG：地址锁存允许/编程脉冲； - PSEN：外部程序存储器选通； - P2.0至P2.7：带有地址线的通用I/O端口。 - **PQFP/TQFP封装**： - 除上述PDIP封装的管脚外，还包含了额外的I/O端口及控制信号。 - **PLCC封装**： - 类似于PDIP封装，但采用了不同的物理布局。 #### 四、AT89C51应用场景 - **消费电子产品**：如家用电器、玩具、遥控器等。 - **工业自动化**：如电机控制、传感器网络、设备监控等。 - **通信设备**：如调制解调器、路由器等。 - **汽车电子**：如车载导航系统、发动机控制单元等。 #### 五、总结 AT89C51作为一款经典的51系列单片机，以其强大的性能、丰富的资源以及广泛的兼容性，在多个领域都有着广泛的应用。对于初学者来说，掌握其基本特性和管脚配置是非常重要的第一步。随着对这款单片机理解的加深，开发者可以利用它来实现更加复杂的功能，满足不同场景下的需求。

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PQFP/TQFP

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

PO.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR)P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

Features

• Compatible with MCS-51

™

Products

• 4K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 24 MHz

• Three-level Program Memory Lock

• 128 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial Channel

• Low-power Idle and Power-down Modes

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K

bytes of Flash programmable and erasable read only memory (PEROM). The device

is manufactured using Atmel’s high-density nonvolatile memory technology and is

compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip

Flash allows the program memory to be reprogrammed in-system or by a conven-

tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash

on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides

a highly-flexible and cost-effective solution to many embedded control applications.

PDIP

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

Rev. 0265G–02/00

8-bit

Microcontroller

with 4K Bytes

Flash

AT89C51

Pin Configurations

PLCC

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

PO.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR)P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1

P1.0

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

AT89C51

The AT89C51 provides the following standard features: 4K

bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit

timer/counters, a five vector two-level interrupt architecture,

a full duplex serial port, on-chip oscillator and clock cir-

cuitry. In addition, the AT89C51 is designed with static logic

for operation down to zero frequency and supports two

software selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM, timer/counters,

serial port and interrupt system to continue functioning. The

Power-down Mode saves the RAM contents but freezes

the oscillator disabling all other chip functions until the next

hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 may also be configured to be the multiplexed low-

order address/data bus during accesses to external pro-

gram and data memory. In this mode P0 has internal

pullups.

Port 0 also receives the code bytes during Flash program-

ming, and outputs the code bytes during program

verification. External pullups are required during program

verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (I

) because of the internal pullups.

Port 1 also receives the low-order address bytes during

Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (I

) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application, it uses strong internal pullups

when emitting 1s. During accesses to external data mem-

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the

contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (I

) because of the pullups.

Port 3 also serves the functions of various special features

of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash pro-

gramming and verification.

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte

of the address during accesses to external memory. This

pin is also the program pulse input (PROG

) during Flash

programming.

In normal operation ALE is emitted at a constant rate of 1/6

the oscillator frequency, and may be used for external tim-

ing or clocking purposes. Note, however, that one ALE

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

(external interrupt 0)

P3.3 INT1

(external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

(external data memory write strobe)

P3.7 RD

(external data memory read strobe)

AT89C51

pulse is skipped during each access to external Data

Memory.

If desired, ALE operation can be disabled by setting bit 0 of

SFR location 8EH. With the bit set, ALE is active only dur-

ing a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

When the AT89C51 is executing code from external pro-

gram memory, PSEN

is activated twice each machine

cycle, except that two PSEN

activations are skipped during

each access to external data memory.

/VPP

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA

will be

internally latched on reset.

should be strapped to V

for internal program

executions.

This pin also receives the 12-volt programming enable volt-

age (V

) during Flash programming, for parts that require

12-volt V

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier which can be configured for use as

an on-chip oscillator, as shown in Figure 1. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 2.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

It should be noted that when idle is terminated by a hard

ware reset, the device normally resumes program execu-

tion, from where it left off, up to two machine cycles before

the internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when Idle is terminated by

reset, the instruction following the one that invokes Idle

should not be one that writes to a port pin or to external

memory.

Figure 1. Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

XTAL2

GND

XTAL1

Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

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