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DFI 3.0规范是针对各种动态随机存取存储器（DRAM）设计的接口标准，包括DDR4、DDR3、DDR2、DDR1以及低功耗DDR2（LPDDR2）和LPDDR1等类型。这一标准由Cadence Design Systems, Inc.开发，旨在规定内存控制器和DRAM之间用于控制信号、时钟、数据和命令传输的物理层接口。从1995年开始，Cadence Design Systems, Inc.逐步发布了多个版本的DFI标准，逐步增加了对不同类型的DRAM支持，并且进行了技术上的改进。从最初的只支持DDR和DDR2的版本，到之后新增的对DDR3的支持，并在后续的版本中不断丰富和完善了对DDR3的支持内容，例如增加了读写校平（leveling）功能。此外，DFI 3.0规范还包含了对低功耗DRAM技术的支持，如LPDDR2。 DFI 3.0规范的重要更新涉及了以下几个方面： 1. 读写校平功能的加入：在校准和优化内存读写操作时，此功能能够对内存时序进行调整，从而提升系统性能。 2. 低功耗控制接口的引入：为了适应越来越普遍的低功耗设备需求，规范中加入了低功耗控制相关的信号和接口定义。 3. 频率变化协议的补充：规范提供了在运行过程中进行频率变化的协议，这允许在不同的频率之间平滑过渡，以便于动态电源管理。 4. 训练操作的改进：包括读训练和写训练操作的优化以及相关的信号定义，确保内存接口在初始化和运行时的稳定性。 5. 增加了对LPDDR2的支持：随着移动设备对功耗和性能的特殊需求，规范中增加了对LPDDR2技术的支持，并对LPDDR2的训练操作进行了相应的规定。在技术细节上，DFI 3.0规范定义了物理接口信号的具体要求，如DFI_RDLVL_EDGE信号用于指示读取校平的边缘触发，而DFI_FREQ_RATIO信号用于描述不同频率间的比率。这些信号的引入和定义，是为了让内存控制器和DRAM之间的通信更加精确和高效。此外，DFI 3.0规范还支持向后兼容，这意味着新的版本在引入新特性的同时，还保留了旧版本的功能，以确保新旧系统间的兼容性和平滑升级。规范也包括了特定模式下的信号定义，如针对DDR3的训练模式信号。更新和维护DFI规范的过程中，Cadence Design Systems, Inc.不断根据技术发展的需求和业界反馈进行调整。例如，在2008年，规范的更新包括了对LPDDR2的初始支持，并修正了2.0版本中的小错误。紧接着，在2009年，DFI规范继续扩展，加入了低功耗控制接口和校平请求信号的定义。到了2010年，DFI 3.0规范进一步丰富了频率比率信息，并增加了奇偶校验接口的参考。 DFI 3.0规范通过详尽的规定，确保内存控制器和DRAM之间能够高效、稳定地进行数据和控制信号的交换，从而让整个系统在各种操作条件下都能保持最佳的性能。随着技术的演进，DFI规范持续更新，以适应新的硬件和应用需求。

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DDR PHY Interface, Version 3.0 1 of 133

Cadence Design Systems, Inc.

DFI

DDR PHY Interface

DFI 3.0 Specification

18 May 2012

2 of 133 DDR PHY Interface, Version 3.0

Cadence Design Systems, Inc.

Release Information

Rev # Date Change

1.0 30 Jan 2007 Initial Release

2.0 17 Jul 2007 Modifications/Additions for DDR3 Support

2.0 21 Nov 2007 Additional modifications/additions for DDR3 support. Added read and

write leveling. Changes approved by the Technical Committee for DDR3

support.

2.0 21 Dec 2007 Removed references to data eye training for PHY Evaluation mode, added

a gate training-specific mode signal, corrected references and clarified

read

training.

2.0 11 Jan 2008 Modified wording; standardized notations in figures, clarified

terminology for read and write leveling.

2.0 26 Mar 2008 Added timing parameter t

rdlvl_en

and t

wrlvl_en

, signal dfi_rdlvl_edge

2.1 2 Oct 2008 Added initial LPDDR2 support and corrected minor errors from 2.0

release

2.1 24 Nov 2008 Added frequency change protocol, signal timing definitions, t

rdlvl_load

and

wrlvl_load

timing parameters and adjusted diagrams accordingly

2.1 30 Jan 2009 Added DFI logo

2.1 31 Mar 2009 Updated width of dfi_rdlvl_edge, corrected erroneous figures, updated

rdlvl_en

and t

wrlvl_en

definitions

2.1 20 May 2009 Added low power control interface, modified leveling request signal

description to include frequency change, added dfi_data_byte_disable

signal and t

phy_wrdata

timing parameters. Added DIMM support to the

status interface and updated frequency ratios from an example to a defined

method. Updated frequency ratios information for new proposals,

modified default values and requirements for some training interface

signals, incorporated LPDDR2 training operations changes

2.1 22 Jun 2009 Expanded frequency ratio information to include vectored read data,

expanded use of dfi_init_start, added timing diagrams for 1:4 frequency

ratio systems

2.1.1 23 Mar 2010 Added reference to the parity interface to the Overview. Changed

dfi_parity_in signal to have a phase index. Modified description of

dfi_freq_ratio signal to make it optional except for MCs/PHYs that

support multiple frequency ratios. Expanded figure 32 into two figures to

represent odd and even timing parameters.

2.1.1 01 Apr 2010 Changed minimum value for t

lp_wakeup

2.1.1 20 Apr 2010 Corrected figure 3 timing violation. Corrected erroneous sentence for 2T

timing. Corrected figure 35 t

phy_wrlat

timing. Correct incorrect references

to t

phy_wrlat

in frequency ratio read examples.

DDR PHY Interface, Version 3.0 3 of 133

Cadence Design Systems, Inc.

2.1.1 27 May 2010 Added Figure 4 and text to explain differences between Figure 3 and 4.

2.1.1 09 Jun 2010 Modified text in dfi_init_start and surrounding figures 3 and 4 for more

clarity.

3.0 21 May 2012 Added DDR4 DRAM support for: CRC, CA parity timing, CRC and CA

parity errors, DBI, leveling support, and CA modifications. Added DFI

read data rotation clarification, read data pointer resynchronization,

independent timing of DFI read data valid per data slice, data path chip

select, error interface, and programmable parameters. Renamed PHY

evaluation mode. Removed MC evaluation mode and t

phy_wrdelay

timing

parameter. Added support for refresh during training, multiple CS

training, enhancements to the update interface and the idle bus definition.

Proprietary Notice

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of Cadence.

Cadence makes no warranties with respect to this documentation and disclaims any implied

warranties of merchantability or fitness for a particular purpose. Information in this document is

subject to change without notice. Cadence assumes no responsibility for any errors that may appear

in this document.

Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly

disclaims, any representations or warranties as to the completeness, accuracy, or usefulness of the

information contained in this document. Cadence does not warrant that use of such information will

not infringe any third party rights, nor does Cadence assume any liability for damages or costs of

any kind that may result from use of such information.

RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in

subparagraphs (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS

252.227-7013.

Destination Control Statement

All technical data contained in this product is subject to the export control laws of the United States

of America. Disclosure to nationals of other countries contrary to United States law is prohibited.

It is the reader's responsibility to determine the applicable regulations and to comply with them.

Trademarks

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.

All other products or brand names mentioned are trademarks or registered trademarks of their

respective holders.

End User License Agreement2

1.Subject to the provisions of Clauses 2, 3, 4, 5 and 6, Cadence hereby grants to licensee

("Licensee") a perpetual, nonexclusive, nontransferable, royalty free, worldwide copyright license

to use and copy the DFI (DDR PHY Interface) specification (the "DFI Specification") for the

purpose of developing, having developed, manufacturing, having manufactured, offering to sell,

selling, supplying or otherwise distributing products which comply with the DFI Specification.

4 of 133 DDR PHY Interface, Version 3.0

Cadence Design Systems, Inc.

2.THE DFI SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES EXPRESS,

IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF

SATISFACTORY QUALITY, MERCHANTABILITY, NONINFRINGEMENT OR FITNESS

FOR A PARTICULAR PURPOSE.

3.No license, express, implied or otherwise, is granted to Licensee, under the provisions of Clause

1, to use Cadence's or any other person or entity participating in the development of the DFI

Specification listed herein (individually "Participant," collectively "Participants") trade name, or

trademarks in connection with the DFI Specification or any products based thereon. Nothing in

Clause 1 shall be construed as authority for Licensee to make any representations on behalf of

Cadence or the other Participants in respect of the DFI Specification.

4.NOTWITHSTANDING ANYTHING ELSE WILL CADENCE'S TOTAL AGGREGATE

LIABILITY FOR ANY CLAIM, SUIT, PROCEEDING OR OTHERWISE, RELATING IN

ANYWAY TO THE DFI SPECIFICATION EXCEED $1.00USD.

5.NOTWITHSTANDING ANYTHING ELSE WILL ANY PARTICIPANT'S TOTAL

AGGREGATE LIABILITY FOR ANY CLAIM, SUIT, PROCEEDING OR OTHERWISE,

RELATING IN ANYWAY TO THE DFI SPECIFICATION EXCEED $1.00USD.

6.Licensee agrees that Cadence and the Participants may use, copy, modify, reproduce and dist-

ribute any written comments or suggestions ("Communications") provided regarding the DFI

Specification by Licensee and that Licensee will not claim any proprietary rights in the DFI

Specification, or implementations thereof by any Participant or third party, as a result of the use of

the Communications in developing or changing the DFI Specification. Cadence and the

participants will have no confidentiality obligations with respect to the Communications and

Licensee will not include any confidential information of Licensee or any third party in any

Communications.

Participants

ARM Cadence Intel LSI Samsung ST Synopsys

DDR PHY Interface, Version 3.0 5 of 133

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CONTENTS

1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.0 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.0 Interface Signal Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.1 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.2 Write Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.1 Write Data Mask/Write DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.2 Write Data Chip Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.3 Write Data CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.2.4 Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.3 Read Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3.1 Read DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3.2 Read Data Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3.3 Read Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.4 Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.4 Update Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.5 Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

3.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

3.5.2 Clock Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.5.3 Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.5.4 Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.5.5 CRC and CA Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3.6 DFI Training Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

3.6.1 Read Training Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

3.6.2 Write Leveling Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

3.6.3 dfi_lvl_pattern Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.6.4 Periodic Training Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

3.7 Low Power Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

3.8 Error Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.0 Functional Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.1 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.2 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

4.3 Data Bus Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

4.4 Write Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.4.1 Write Transaction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

4.4.2 DBI - Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.4.3 Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.4.3.1 MC CRC Support (phycrc_mode ==0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.4.3.2 PHY CRC Support (phycrc_mode ==1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4.4.3.3 Burst Chop 4 with PHY CRC Support (phycrc_mode ==1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.5 Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79