vscode搭建32位MCU开发环境

//////////////////////////////////////////////////////////////////////////////// /// @file hal_tim.c /// @author AE TEAM /// @brief THIS FILE PROVIDES ALL THE TIM FIRMWARE FUNCTIONS. //////////////////////////////////////////////////////////////////////////////// /// @attention /// /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. /// /// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2> //////////////////////////////////////////////////////////////////////////////// // Define to prevent recursive inclusion #define _HAL_TIM_C_ // Files includes #include "hal_rcc.h" #include "hal_tim.h" //////////////////////////////////////////////////////////////////////////////// /// @addtogroup MM32_Hardware_Abstract_Layer /// @{ //////////////////////////////////////////////////////////////////////////////// /// @addtogroup TIM_HAL /// @{ //////////////////////////////////////////////////////////////////////////////// /// @addtogroup TIM_Exported_Functions /// @{ //////////////////////////////////////////////////////////////////////////////// /// @brief Deinitializes the tim peripheral registers to their default reset values. /// @param tim: select the TIM peripheral. /// @retval None. //////////////////////////////////////////////////////////////////////////////// void TIM_DeInit(TIM_TypeDef* tim) { switch (*(vu32*)&tim) { case (u32)TIM1: exRCC_APB2PeriphReset(RCC_APB2ENR_TIM1); break; case (u32)TIM2: exRCC_APB1PeriphReset(RCC_APB1ENR_TIM2); break; case (u32)TIM3: exRCC_APB1PeriphReset(RCC_APB1ENR_TIM3); break; case (u32)TIM4: exRCC_APB1PeriphReset(RCC_APB1ENR_TIM4); break; case (u32)TIM5: exRCC_APB1PeriphReset(RCC_APB1ENR_TIM5); break; case (u32)TIM6: exRCC_APB1PeriphReset(RCC_APB1ENR_TIM6); break; case (u32)TIM7: exRCC_APB1PeriphReset(RCC_APB1ENR_TIM7); break; case (u32)TIM8: exRCC_APB2PeriphReset(RCC_APB2ENR_TIM8); break; default: break; } } //////////////////////////////////////////////////////////////////////////////// /// @brief Initializes the tim Time Base Unit peripheral according to /// the specified parameters in the init_struct. /// @param tim: select the TIM peripheral. /// @param init_struct: pointer to a TIM_TimeBaseInitTypeDef /// structure that contains the configuration information for the /// specified TIM peripheral. /// @retval None. //////////////////////////////////////////////////////////////////////////////// void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct) { MODIFY_REG(tim->CR1, TIM_CR1_CKD, init_struct->TIM_ClockDivision); if ((tim == TIM1) || (tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM8)) MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, init_struct->TIM_CounterMode); if ((tim == TIM1) || (tim == TIM8) ) MODIFY_REG(tim->RCR, TIM_RCR_REP, init_struct->TIM_RepetitionCounter); WRITE_REG(tim->ARR, init_struct->TIM_Period); WRITE_REG(tim->PSC, init_struct->TIM_Prescaler); WRITE_REG(tim->EGR, TIM_PSCReloadMode_Immediate); } //////////////////////////////////////////////////////////////////////////////// /// @brief Initializes the tim Channel1 according to the specified /// parameters in the init_struct. /// @param tim: select the TIM peripheral. /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that /// contains the configuration information for the specified TIM peripheral. /// @retval None. //////////////////////////////////////////////////////////////////////////////// void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) { MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, init_struct->TIM_OCMode); MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC1EN, \ ((u32)init_struct->TIM_OCPolarity) | ((u32)init_struct->TIM_OutputState)); WRITE_REG(tim->CCR1, init_struct->TIM_Pulse); if ((tim == TIM1) || (tim == TIM8)) { MODIFY_REG(tim->CCER, TIM_CCER_CC1NP | TIM_CCER_CC1NEN, \ ((u32)init_struct->TIM_OCNPolarity) | ((u32)init_struct->TIM_OutputNState)); MODIFY_REG(tim->CR2, TIM_CR2_OIS1 | TIM_CR2_OIS1N, \ ((u32)init_struct->TIM_OCIdleState) | ((u32)init_struct->TIM_OCNIdleState)); } } //////////////////////////////////////////////////////////////////////////////// /// @brief Initializes the tim Channel2 according to the specified /// parameters in the init_struct. /// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that /// contains the configuration information for the specified TIM peripheral. /// @retval None. //////////////////////////////////////////////////////////////////////////////// void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) { MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, init_struct->TIM_OCMode << 8); MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, \ (init_struct->TIM_OCPolarity << 4) | (init_struct->TIM_OutputState << 4)); WRITE_REG(tim->CCR2, init_struct->TIM_Pulse); if ((tim == TIM1) || (tim == TIM8)) { MODIFY_REG(tim->CCER, TIM_CCER_CC2NP | TIM_CCER_CC2NEN, \ (init_struct->TIM_OCNPolarity << 4) | (init_struct->TIM_OutputNState << 4)); MODIFY_REG(tim->CR2, TIM_CR2_OIS2 | TIM_CR2_OIS2N, \ (init_struct->TIM_OCIdleState << 2) | (init_struct->TIM_OCNIdleState << 2)); } } //////////////////////////////////////////////////////////////////////////////// /// @brief Initializes the tim Channel3 according to the specified /// parameters in the init_struct. /// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that /// contains the configuration information for the specified TIM peripheral. /// @retval None. //////////////////////////////////////////////////////////////////////////////// void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) { MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, init_struct->TIM_OCMode); MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, \ (init_struct->TIM_OCPolarity << 8) | (init_struct->TIM_OutputState << 8)); WRITE_REG(tim->CCR3, init_struct->TIM_Pulse); if ((tim == TIM1) || (tim == TIM8)) { MODIFY_REG(tim->CCER, TIM_CCER_CC3NP | TIM_CCER_CC3NEN, \ (init_struct->TIM_OCNPolarity << 8) | (init_struct->TIM_OutputNState << 8)); MODIFY_REG(tim->CR2, TIM_CR2_OIS3 | TIM_CR2_OIS3N, \ (init_struct->TIM_OCIdleState << 4) | (init_struct->TIM_OCNIdleState << 4)); } } //////////////////////////////////////////////////////////////////////////////// /// @brief Initializes the tim Channel4 according to the specified /// parameters in the init_struct. /// @param tim:select the TIM peripheral. /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that /// contains the configuration information for the specified TIM peripheral. /// @retval None. /////////////////