JEDEC Publication No. 157A
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RECOMMEND ESD-CDM TARGET LEVELS
Foreword
CDM has become the primary real-world ESD event metric describing ESD charging and rapid discharge
events in automated handling, manufacturing, and assembly of IC devices. Its importance has
dramatically increased over the years as package feature sizes, capacitance, and pin count have scaled
upward. In years past, arbitrary CDM protection levels had been specified as IC qualification goals with
little background information available on actual/realistic CDM event levels and the protection methods
available in manufacturing controls and device design for the safe production of IC components. The
rapid advancement of IC technology scaling, coupled with the increased demand for high-speed circuit
performance, made it increasingly difficult to guarantee a customer-specified “500 volts” CDM
specification and as this update will discuss, even 250 volts can create challenges. At the same time, the
required static control methods available for production area CDM protection at each process step have
not been fully outlined. Therefore, a realistic CDM specification target must be defined in terms of
available and commonly practiced CDM control methods and must reflect current ESD design
constraints. Additionally, as technology scaling continues, very high-speed I/Os are being introduced
which demand the need for lower CDM target levels in order to achieve the needed I/O performance. This
is the scope of this latest update to JEP157.
By balancing improved static ESD controls specific to CDM, and limited ESD design capability in
today’s leading technologies, we recommend a CDM specification target level of 250 volts with
consideration for lower CDM target levels in unique cases where very high-speed I/O performance is
needed. These target levels are a realistic and safe CDM level for manufacturing and handling today’s
products using basic CDM control methods or advanced CDM control techniques as needed based on the
target level.
At the same time, we show that the current trend of silicon technology scaling will continue to place
further restrictions on achievable CDM levels. It is, therefore, necessary that the Industry Council
presents a realistic CDM roadmap for consideration by the industry moving forward to 7 nm technologies
and beyond, including 2.5D and 3D technologies.
Introduction
It is well understood in the IC industry that the charged device model (CDM) is the ESD model that best
describes real-world component-level ESD events during IC manufacturing and handling.
See Clause 4
for details. In contrast to HBM, where basic ESD control measures in manufacturing ensure a safe and
realistic specification level (i.e. 1000 volts HBM as reported in JEP155 [1]), CDM protection requires
these basic ESD controls as well as additional ESD controls such as managing against the charging of
insulators, at specific process steps, to ensure safe and realistic levels for all product designs below 200
volts. Some of these additional process assessment techniques that may need to be involved are detailed
out in a recently released standard practice from the ESDA entitled “Protection of Electrostatic Discharge
Susceptible Items – Process Assessment Techniques”, ANSI/ESD SP17.1. As IC applications have
moved towards ultra-high-speed I/O interfaces (> 200 Gb/s) over the last decade, this CDM threat has
been further exacerbated in terms of qualification levels to achieve design performance. This has driven
the need for advanced control methods to be implemented for safe manufacturing in the production area.
Combined with these new developments the sensitivity and accuracy for CDM testing have become more
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