CXL_white_paper.pdf
需积分: 50 199 浏览量
2020-05-03
20:17:38
上传
评论
收藏 289KB PDF 举报
Compute Express Link
Dr. Debendra Das Sharma
Intel Fellow and Director, I/O Technology and Standards
Promoter Member, Compute Express Link
Compute Express Link (CXL) is an open industry standard interconnect offering high-bandwidth, low-
latency connectivity between host processor and devices such as accelerators, memory buffers, and
smart I/O devices. CXL is based on the PCI Express® (PCIe®) 5.0 physical layer infrastructure. It is
designed to address the growing high-performance computational workloads by supporting
heterogeneous processing and memory systems with applications in Artificial Intelligence, Machine
Learning, communication systems, and High Performance Computing by enabling coherency and
memory semantics. This is increasingly important as processing data in these emerging applications
requires a diverse mix of scalar, vector, matrix and spatial architectures deployed in CPU, GPU, FPGA,
smart NICs, and other accelerators.
CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CXL.io, based on
PCIe®), caching (CXL.cache) and memory (CXL.memory) semantics. CXL maintains a unified, coherent
memory space between the CPU (host processor) and any memory on the attached CXL device. This
allows both the CPU and device to share resources for higher performance and reduced software stack
complexity. Moreover, since the CPU is primarily responsible for coherency management, it can reduce
device cost and complexity, as well as overhead traditionally associated with coherency across an I/O
link.
CXL runs on PCIe® PHY and supports x16, x8, and x4 link widths natively and x2 and x1 widths in
degraded mode. CXL 1.0 will debut at 32 GT/s, offering 64 GB/s bandwidth in each direction. CXL 1.0
also supports 16.0 GT/s and 8.0 GT/s data rates in degraded mode. The following diagram illustrates
how CXL offers full interoperability with PCIe since it uses the PCIe stack. A CXL device starts link training
in PCIe Gen 1 Data Rate and negotiates CXL as the operating protocol using the alternate protocol
negotiation mechanism defined in the PCIe 5.0 specification, if its link partner is capable of supporting
CXL. Leveraging the PCIe 5.0 infrastructure makes it really easy for devices and platforms to adopt CXL
without having to design and validate the PHY, channel, any channel extension devices such as Retimers,
or the upper layers of PCIe, including the software stack.
评论0
最新资源