There is a massive overhead of designs with standard cells. Every gate has to have inverter at the input, there is virtually no sharing of diffusion. The biggest problem is that yeah one can layout a big design through these algorithms but still it has to be relatively small.
a) RTL level netlist [ Verilog ,Modelsim ]
b) Convert into gates after synthesis. [ DC compiler ]
c) Import into Cadence and then try to optimize the layouts. [ Understanding of Virtouso]
d) Verify the timing with Nanotime and spice.
The book is good as far as message it is conveying but the problem is that the layout tool has to be "very very" good in handling the layouts. At this point, there are no commercial tools for doing this layout because the biggest problem is timing. A person/group who is trying this method has to have expertise in all the aspects which in industry is compartmentilzed ( RTL team , PD team and stdcell team ) with clear demarcations. This makes the implementation very difficult. But a change has to happen to implement this to get better designs for relatively smaller designs.
There is company called nangate.com which does some similar but it ends up generating so many "fine" grain cells that timing characterization for the synopsys libraries becomes excessivly time taking and it is something which is not a very good idea.
