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EP4CE10F17C8 pin配置指南
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PCG-01008-1.6
Copyright © 2013 Altera Corp.
Disclaimer Page 1 of 14
Cyclone
®
IV Device Family Pin Connection Guidelines
PCG-01008-1.6
© 2013 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all
other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under
numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to
current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
These pin connection guidelines should only be used as a recommendation, not as a specification.
The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.
PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THE PIN CONNECTION GUIDELINES ("GUIDELINES")
PROVIDED TO YOU. BY USING THESE GUIDELINES, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE
THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN YOU AND ALTERA CORPORATION ("ALTERA"). IF YOU DO NOT AGREE WITH ANY OF
THESE TERMS AND CONDITIONS, DO NOT DOWNLOAD, COPY, INSTALL, OR USE THESE GUIDELINES.
1. Subject to the terms and conditions of this Agreement, Altera grants to you the use of this pin connection guideline to determine the pin connections of an
Altera
®
programmable logic device-based design. You may not use this pin connection guideline for any other purpose.
2. Altera does not guarantee or imply the reliability, or serviceability, of the pin connection guidelines or other items provided as part of these guidelines. The
files contained herein are provided 'AS IS'. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
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Pin Connection Guidelines Agreement © 2013 Altera Corporation. All rights reserved.
PCG-01008-1.6
Copyright © 2013 Altera Corp.
Pin Connection Guidelines Page 2 of 14
Cyclone GX IV Devices Pin Name
Cyclone IV E Devices Pin
Name
Pin Type (1st, 2nd, and
3rd Function)
Pin Description Connection Guidelines
CLK[5, 7, 9, 11, 12, 14, 17, 19, 20,
22], DIFFCLK_[0..9]p (Note 9)
REFCLK[0..5]p (Note 22), (Note
24)
CLK[2,4,6,9,11,13,15],
DIFFCLK_[1..7]p (Note 9)
Clock, Input
Dedicated global clock input pins that can also be used for the positive terminal inputs for
differential global clock input or user input pins.
In Cyclone IV GX devices, some of these pins are optional high speed differential reference clock
positive input.
Connect unused CLK or DIFFCLK pins to GND. See Note 12.
In Cyclone IV GX devices, the pin should be AC-coupled if used as optional high speed differential reference clock input.
Connect all unused pins either individually to GND through a 10-KΩ resistor or tie all unused pins together through a single 10-
KΩ resistor. Ensure that the trace from the pins to the resistor(s) is as short as possible.
CLK[4, 6, 8, 10, 13, 15, 16, 18, 21,
23], DIFFCLK_[0..9]n (Note 9)
REFCLK[0..5]n (Note 22), (Note
24)
CLK[1,3,5,7,8,10,12,14],
DIFFCLK_[1..7]n (Note 9)
Clock, Input
Dedicated global clock input pins that can also be used for the negative terminal inputs for
differential global clock input or user input pins.
In Cyclone IV GX devices, some of these pins are optional high speed differential reference clock
complement input.
Connect unused CLK or DIFFCLK pins to GND. See Note 12.
In Cyclone IV GX devices, the pin should be AC-coupled if used as optional high speed differential reference clock input.
Connect all unused pins either individually to GND through a 10-KΩ resistor or tie all unused pins together through a single 10-
KΩ resistor. Ensure that the trace from the pins to the resistor(s) is as short as possible.
PLL[1,2,3,4,5,8]_CLKOUTp
(Note 10)
PLL[1..4]_CLKOUTp (Note 10)
I/O, Output
Optional positive terminal for external clock outputs from PLL [1..8] in Cyclone IV GX devices.
Optional positive terminal for external clock outputs from PLL [1..4] in Cyclone IV E devices.
Each pin can be assigned to single-ended or differential I/O standards if it is being fed by a PLL
output.
When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as
defined in Quartus II software. See Note 12.
PLL[1,2,3,4,5,8]_CLKOUTn
(Note 10)
PLL[1..4]_CLKOUTn (Note 10)
I/O, Output
Optional negative terminal for external clock outputs from PLL [1..8] in Cyclone IV GX devices.
Optional negative terminal for external clock outputs from PLL [1..4] in Cyclone IV E devices.
Each pin can be assigned to single-ended or differential I/O standards if it is being fed by a PLL
output.
When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as
defined in Quartus II software. See Note 12.
MSEL[0..3] MSEL[0..3] Input
Configuration input pins that set the Cyclone IV device configuration scheme. The smaller
Cyclone IV GX devices like EP4CGX15, EP4CGX22, and EP4CGX30 (F324, F169 package) do
not have the MSEL[3] pin. Some of the smaller Cyclone IV E devices or package options do not
support AP configuration scheme and do not have the MSEL[3] pin.
These pins are internally connected through a 9-KΩ resistor to GND. Do not leave these pins floating. When these pins are
unused, connect them to GND. Depending on the configuration scheme used, these pins should be tied to VCCA or GND.
Refer to the "Configuration and Remote System Upgrades in Cyclone IV Devices" chapter in the Cyclone IV Handbook. If only
JTAG configuration is used, connect these pins to GND.
nCE nCE Input
Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high,
the device is disabled.
In a multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the
chain. In single device configuration and JTAG programming, nCE should be connected to GND.
nCONFIG nCONFIG Input
Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA
to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a
logic high level will initiate reconfiguration.
If you are using PS configuration scheme with a download cable, connect this pin through a 10-KΩ resistor to VCCA. For
other configuration schemes, if this pin is not used, this pin must be connected directly or through a 10-KΩ resistor to VCCIO.
CONF_DONE CONF_DONE Bidirectional
(open-drain)
This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low
before and during configuration. Once all configuration data is received without error and the
initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high
after all data is received. Then the device initializes and enters user mode.
This pin is not available as a user I/O pin. CONF_DONE should be pulled high by an external 10-KΩ pull-up resistor.
nCEO (Note 24) nCEO I/O, Output
(open-drain)
Output that drives low when device configuration is complete. This pin can be used as a regular
I/O if not used for device configuration.
When not using this pin, you can leave it unconnected. During multi-device configuration, this pin feeds the nCE pin of a
subsequent device. In this case, tie the 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain which
satisfies the input voltage of the receiving device. During single device configuration, this pin can be used as a regular I/O.
nSTATUS nSTATUS Bidirectional
(open-drain)
This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after
power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an
error occurs during configuration. As a status input, the device enters an error state when
nSTATUS is driven low by an external source during configuration or initialization.
This pin is not available as a user I/O pin. nSTATUS should be pulled high by an external 10-KΩ pull-up resistor.
TCK TCK Input Dedicated JTAG test clock input pin. Connect this pin to a 1-KΩ pull-down resistor to GND. To disable the JTAG circuitry connect TCK to GND.
TMS TMS Input Dedicated JTAG test mode select input pin. Connect this pin to a 1-KΩ to 10-KΩ pull-up resistor to VCCA. (Note 13) To disable the JTAG circuitry connect TMS to VCCA.
TDI TDI Input Dedicated JTAG test data input pin. Connect this pin to a 1-KΩ to 10-KΩ pull-up resistor to VCCA. (Note 13) To disable the JTAG circuitry connect TDI to VCCA.
TDO TDO Output Dedicated JTAG test data output pin. If the TDO pin is not used, leave this pin unconnected.
nCSO (Note 24) FLASH_nCE, nCSO
I/O, Output (AS, AP Note
18)
This pin functions as FLASH_nCE in AP (Note 18) mode, and nCSO in AS mode.
nCSO: Output control signal from the FPGA to the serial configuration device in AS mode that
enables the configuration device.
FLASH_nCE: Output control signal from the FPGA to the parallel flash in AP mode that enables
the flash device.
When not programming the device in AS mode, nCSO is not used. When not programming the device in AP mode,
FLASH_nCE is not used. If the pin is not used as an I/O, you should leave the pin unconnected.
DATA1, ASDO (Note 24) DATA1, ASDO
Input (FPP)
Output (AS)
Bidirectional (AP Note 18)
This pin functions as DATA1 in PS and FPP modes, and as ASDO in AS mode.
DATA1: Data input in non-AS mode. Byte-wide configuration data is presented to the target
device on DATA[0..7].
In PS configuration scheme, DATA1 functions as user I/O pin during configuration, which means
it is tri-stated. After FPP configuration, DATA1 is available as a user I/O pin and the state of this
pin depends on the Dual- Purpose Pin settings.
ASDO: Control signal from the FPGA to the serial configuration device in AS mode used to read
out configuration data.
When not programming the device in AS mode, this pin is available as a user I/O pin. If the pin is not used as an I/O, then you
should leave the pin unconnected.
DATA[2..7] DATA[2..7]
Input (FPP)
Bidirectional (AP Note 18)
Data inputs. Byte-wide or word-wide configuration data is presented to the target device on
DATA[0..7] or DATA[0..15] respectively. In AS or PS configuration scheme, they function as user
I/O pins during configuration, which means they are tri-stated. After FPP configuration, DATA
[2..7] are available as user I/O pins and the state of these pins depends on the Dual-Purpose Pin
settings.
When not programming the device in AP mode, these pins are available as a user I/O pins. If the pin is not used as an I/O you
should leave the pin unconnected.
NA DATA[8..15] Bidirectional (AP Note 18)
In the PS, FPP, or AS configuration scheme, they function as user I/O pins during configuration,
which means they are tri-stated.
After AP configuration, DATA[8..15] are dedicated bidirectional pins with optional user control.
When not programming the device in AP mode, these pins are available as user I/O pins. If these pins are not used as I/Os,
then it is recommended to leave the pin unconnected.
NA PADD[0..23] Output (AP Note 18) 24-bit address bus from the Cyclone IV E device to the parallel flash in AP mode.
When not programming the device in AP mode, these pins are available as user I/O pins. If these pins are not used as I/Os,
then it is recommended to leave the pin unconnected.
NA nRESET Output (AP Note 18) Active-low reset output. Driving the nRESET pin low resets the parallel flash.
When not programming the device in AP mode, nRESET is not used and is available as a user I/O pin. If the pin is not used
as an I/O then it is recommended to leave the pin unconnected.
Cyclone
®
IV Device Family Pin Connection Guidelines
PCG-01008-1.6
Clock and PLL Pins
Create a Quartus
®
II design, enter your device I/O assignments and compile the design. The Quartus II software will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package,
I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Configuration/ JTAG Pins
PCG-01008-1.6
Copyright © 2013 Altera Corp.
Pin Connection Guidelines Page 3 of 14
Cyclone GX IV Devices Pin Name
Cyclone IV E Devices Pin
Name
Pin Type (1st, 2nd, and
3rd Function)
Pin Description Connection Guidelines
Cyclone
®
IV Device Family Pin Connection Guidelines
PCG-01008-1.6
Create a Quartus
®
II design, enter your device I/O assignments and compile the design. The Quartus II software will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package,
I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
NA nAVD Output (AP Note 18)
Active-low address valid output. Driving the nAVD pin low during read or write operation indicates
to the parallel flash that valid address is present on the PADD[0..23] address bus.
When not programming the device in AP mode, nAVD is not used and is available as a user I/O pin. If the pin is not used as
an I/O then it is recommended to leave the pin unconnected.
NA nOE Output (AP Note 18)
Active-low output enable to the parallel flash. Driving the nOE pin low during read operation
enables the parallel flash outputs (DATA[0..15] and RDY).
When not programming the device in AP mode, nOE is not used and is available as a user I/O pin. If the pin is not used as an
I/O then it is recommended to leave the pin unconnected.
NA nWE Output (AP Note 18)
Active-low write enable to the parallel flash. Driving the nWE pin low during write operation
indicates to the parallel flash that data on the DATA[0..15] bus is valid.
When not programming the device in AP mode, nWE is not used and is available as a user I/O pin. If the pin is not used as an
I/O then it is recommended to leave the pin unconnected.
DCLK DCLK
Input (PS, FPP)
Output (AS, AP Note 18)
Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock
configuration data from an external source into the FPGA. In AS and AP (Note 18) modes,
DCLK is an output from the FPGA that provides timing for the configuration interface.
Do not leave this pin floating. Drive this pin either high or low. You can configure DCLK as a user IO only after active serial
configuration.
CRC_ERROR
CRC_ERROR (Note 19 and 21) I/O, Output
Active high signal that indicates that the error detection circuit has detected errors in the
configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is
enabled. This pin can be used as regular I/O if not used for CRC error detection. The
CRC_ERROR pin is an open-drain output powered by 10k pull-up in Cyclone IV GX devices.
When using this pin, connect it to an external 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain that
satisfies the input voltage of the receiving device. When not using this pin, it can be left floating.
DEV_CLRn DEV_CLRn
I/O (when option off),
Input (when option on)
Optional pin that allows designers to override all clears on all device registers. When this pin is
driven low, all registers are cleared; when this pin is driven high, all registers behave as
programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option
in the Quartus II software.
When the dedicated input DEV_CLRn is not used and this pin is not used as an I/O, tie this pin to GND.
DEV_OE DEV_OE
I/O (when option off),
Input (when option on)
Optional pin that allows designers to override all tri-states on the device. When this pin is driven
low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the
design. This pin is enabled by turning on the Enable device-wide output enable (DEV_OE) option
in the Quartus II software.
When the dedicated input DEV_OE is not used and this pin is not used as an I/O, then you should tie this pin to GND.
DATA0 (Note 24) DATA0
Input (PS, FPP, AS)
Bidirectional
(AP Note 18)
Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data
is received through this pin.
After AS configuration, DATA0 is a dedicated input pin with optional user control.
After PS or FPP configuration, DATA0 is available as a user I/O pin and the state of this pin
depends on the Dual-Purpose Pin settings.
After AP (Note 18) configuration, DATA0 is a dedicated bidirectional pin with optional user
control.
If you are using a serial configuration device in AS configuration mode, you must connect a 25-Ω series resistor at the near
end of the serial configuration device for the DATA0. When the dedicated input for DATA0 is not used and this pin is not used
as an I/O, then you should to leave this pin unconnected.
INIT_DONE (Note 24) INIT_DONE
I/O, Output
(open-drain)
This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE.
When enabled, a transition from low to high at the pin indicates when the device has entered
user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user
I/O pin after configuration. This pin is enabled by turning on the Enable INIT_DONE output
option in the Quartus II software.
When using this pin, connect it to an external 10-KΩ pull-up resistor to an acceptable voltage for all devices in the chain that
satisfies the input voltage of the receiving device. When not using this pin, it can be left floating or tied to GND.
CLKUSR (Note 24) CLKUSR I/O, Input
Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this
pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin.
This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the
Quartus II software.
If the CLKUSR pin is not used as a configuration clock input and the pin is not used as an I/O, then you should connect this
pin to GND.
DIFFIO_[R,T,B][0..72][p,n] (Note
14)
DIFFIO_[L,R,T,B][0..61][p,n]
(Note 14)
I/O, TX/RX channel
Dual-purpose differential transmitter/receiver channels. These channels can be used for
transmitting/receiving LVDS compatible signals. Pins with a "p" suffix carry the positive signal for
the differential channel. Pins with an "n" suffix carry the negative signal for the differential
channel. If not used for differential signaling, these pins are available as user I/O pins.
When these IO pins are not used, they can be tied to GND. See Note 12.
DQS[0..5][R,T,B]/CQ[0,1,3,5][R,T,B
]#,DPCLK[0..17] (Note 15)
DQS[0..5][L,R,T,B]/CQ[1,3,5]
[L,R,T,B][#],DPCLK[0..11] (Note
15)
I/O, DQS/CQ, DPCLK
Dual-purpose DPCLK/DQS pins can connect to the global clock network for high-fanout control
signals such as clocks, asynchronous clears, presets and clock enables. It can also be used as
optional data strobe signal for use in external memory interfacing. These pins drive to dedicated
DQS phase shift circuitry, which allows fine tune of the phase shift for input clocks or strobes to
properly align clock edges needed to capture data.
When these IO pins are not used, they can be tied to GND. See Note 12.
NA
DQS[0..5][L,R,T,B]/CQ[1,3,5]
[L,R,T,B][#],CDPCLK[0..7]
(Note 15)
I/O, DQS/CQ,CDPCLK
Dual-purpose CDPCLK/DQS pins can connect to the global clock network for high fan-out
control signals such as clocks, asynchronous clears, presets, and clock enables. Only one of the
two CDPCLK in each corner can feed the clock control block at a time. The other pin can be
used as general-purpose I/O pin. The CDPCLK signals incur more delay to the clock block
control because they are multiplexed before driving into the clock block control. It can also be
used as optional data strobe signal for use in external memory interfacing. These pins drive to
dedicated DQS phase shift circuitry, which allows fine tune of the phase shift for input clocks or
strobes to properly align clock edges needed to capture data.
When these IO pins are not used, they can be tied to GND. See Note 12.
DQ[0..5][R,T,B] (Note 15) DQ[0..5][L,R,T,B] (Note 15) I/O, DQ
Optional data signal for use in external memory interface. When these IO pins are not used, they can be tied to GND. See Note 12.
DM[0..5][R,T,B]/BWS#[0..5][R,T,B]
DM[0..5][L,R,B,T][0..1]/
BWS#[0..5][L,R,T,B]
I/O, DM/BWS#
The data mask pins are only required when writing to DDR SDRAM and DDR2 SDRAM devices.
QDRII SRAM devices use the BWS signal to select the byte to be written into memory. A low
signal on the DM/BWS# pin indicates that the write is valid. Driving the DM/BWS# pin high
results in the memory masking the DQ signals.
When these IO pins are not used ,they can be tied to GND. See Note 12.
RUP[2..4] RUP[1..4] I/O, Input
Reference pins for on-chip termination (OCT) block in I/O banks 4, 5, and 7 in Cyclone IV GX
devices. Reference pins for OCT block in I/O banks 2, 4, 5, and 7 in Cyclone IV E devices. The
external precision resistor RUP must be connected to the designated RUP pin within the same
bank when used. If the RUP pin is not used, this pin can function as a regular I/O pin.
When using OCT tie these pins to the required banks VCCIO through either a 25 Ω or 50 Ω resistor, depending on the desired
I/O standard. When the device does not use this dedicated input for the external precision resistor or as an I/O, it is
recommended that the pin be connected to VCCIO of the bank in which the RUP pin resides or GND.
RDN[2..4] RDN[1..4] I/O, Input
Reference pins for on-chip termination (OCT) block in I/O banks 4, 5, and 7 in Cyclone IV GX
devices. Reference pins for OCT block in I/O banks 2, 4, 5, and 7 in Cyclone IV E devices. The
external precision resistor RDN must be connected to the designated RDN pin within the same
bank when used. If the RDN pin is not used, this pin can function as a regular I/O pin.
When using OCT tie these pins to GND through either a 25 Ω or 50 Ω resistor depending on the desired I/O standard. When
the device does not use this dedicated input for the external precision resistor or as an I/O, it is recommended that the pin be
connected to GND.
Differential I/O Pins
External Memory Interface Pins
Reference Pins
例如DIFFIO_T10p
片上匹配阻抗
双用途DPCLK/DQS引脚可以连接到全球时钟网络,用于高扇出控制信号,如时钟,异步清除,预设和时钟启用。
它也可以用作可选的数据频闪信号,用于外部存储器接口。这些引脚驱动专用 DQS相移电路,允许微调输入时
钟或频闪灯的相移正确对齐时钟边缘需要捕获数据
剩余13页未读,继续阅读
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