EDA 2位频率计设计
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2009-12-01
23:17:26
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1：cnt210.vhd 有时钟使能的十进制计数器源程序：
library work;
library std;
library work;
library std;
library ieee;
use ieee.std_logic_1164.all;
entity cnt210 is
port(clk:in std_logic;
clr:in std_logic;
ena:in std_logic;
cq:out integer range 0 to 15;
carry_out:out std_logic);
end entity cnt210;
architecture art of cnt210 is
signal cqi:integer range 0 to 15;
begin
process(clk,clr,ena)is
begin
if clr='1' then cqi<=0;elsif clk'event and clk='1' then
if ena='1' then
if cqi<9 then cqi<=cqi+1;else cqi<=0;
end if;
end if;
end if;
end process;
process(cqi) is
begin
if cqi=9 then carry_out<='1';else carry_out<='0';end if;
end process;
cq<=cqi;
end architecture art;
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