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3/6/2012 PJ87F

Data Sheet

BCM5396

5396-DS113-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 February 07, 2012

Single-Chip 16-Port SerDes Gigabit Switch

GENERAL DESCRIPTION

FEATURES

The BCM5396 is a 16-port Gigabit Ethernet (GbE)

switch integrated with 16 1.25G SerDes/SGMII port

interfaces for connecting to external Gigabit PHYs or

fiber modules. The BCM5396 provides the lowest-

cost GbE functionality to the desktop switching

solution or WebSmart™ application.

The BCM5396 is a highly integrated solution,

combining all of the functions of a high-speed switch

system, including packet buffer, Media Access

Controllers (MACs), address management, and a non-

blocking switch controller into a single monolithic

0.13 µm CMOS device. The BCM5396 complies with

the IEEE 802.3™, 802.3u, 802.3ab, and 802.3x

specifications, including the MAC control PAUSE

frame and auto-negotiation subsections, providing

compatibility with all industry-standard Ethernet,

Fast Ethernet, and GbE devices.

The BCM5396 device provides integrated 1.25G

SerDes, reducing board footprint requirements. The

16 ports have SGMII interfaces for connecting with

external GbE transceivers.

• 16-port 10/100/1000 Mbps integrated switch

controller via 1.25G SerDes/SGMII/fiber

• Embedded 256 KB on-chip packet buffer

• One 10/100/1000 Mbps In-band Management

Port (IMP) with GMII/RGMII/RvMII/MII interface

for PHY-less connection to a CPU/management

entity (for management purposes only)

• Integrated address management

• Supports up to 4K MAC addresses

• Supports jumbo frames up to 9728 bytes.

• Supports EEPROM for low-cost chip configuration

• Integrated Motorola® SPI-compatible interface

• Supports port mirroring

• Port-based VLAN and 4K IEEE 802.1Q tag VLAN

• Port-, DiffServ-, MAC-, and IEEE 802.1p-based QoS

for four queues

• Supports Spanning Tree, Rapid Spanning Tree, and

Multiple Spanning Tree protocols (802.1D/1s/1w)

• Supports IEEE Standard 802.1X port security

• Supports pseudo-PHY MDIO access

• MAC-based trunking with link fail-over

• Ethernet-in-the-last-mile (EFM) support: OAM and

• Low-power (2.2W total) 1.2V core/2.5V (SGMII I/

O)/3.3V (GMII/MII/RvMII) and 2.5V RGMII

operation with 3.3V I/O tolerance

• 256-pin FBGA package

3/6/2012 PJ87F

Revision HistoryBCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 2

Figure 1: Functional Block Diagram

Deserializer/

Serializer

Deserializer/

Serializer

Deserializer/

Serializer

Gigabit MAC

Internal

Regulators

Space

Internal

Memory

Address

Management

Gigabit MAC

GMII/RGMII/MII/RvMII

Interface

MDC/MDIO

Interface

Configuration

Pins

SPI Interface or

EEPROM Interface

SerDes

Interface

Port 0

SerDes

Interface

Port 1

SerDes

Interface

Port 15

3/6/2012 PJ87F

Revision HistoryBCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 3

Revision History

Revision Date Change Description

5396-DS113-R 02/07/12 Updated:

• Table 93: “Internal SerDes Registers Page Descriptions 10h–1Fh,” on

page 127.

• Table 94: “Internal SerDes Registers Page 10h–1Fh,” on page 127.

• Table 144: “New Priority Map Register (Pages 34h: Address 0C–0Fh),” on

page 163.

5396-DS112-R 06/10/10 Updated:

• Table 144: “Auto-Negotiation Link Partner Ability (Page 10h–1Fh:

Address 0Ah–0Bh),” on page 153.

• “PRBS Status Register (Page 10h ~ 1Fh: Address 32h ~ 33h)” on page 166.

5396-DS111-R 08/26/09 Updated:

• Section 12: “Ordering Information,” on page 175.

5396-DS110-R 02/25/08 Updated:

• “Signal Descriptions” on page 54: BIST_CLRMEM_SEL and SKIP_MEMBIST

descriptions.

Removed:

• References to behavior of management frames in unmanaged mode

5396-DS109-R 11/13/07 Updated:

• “Management Frames” on page 24, and “Frame Management” on

page 32: Corrected terminology relating to the in-band management

port.

• Table 59, “Management Mode Registers (Page 02h),” on page 81:

Changed definition of bits 7:6.

Added:

• “In-Band Management Port” on page 33: Added note.

• Table 23, “Signal Descriptions,” on page 53 and “Pin Assignments” on

page 58: Added BIST_CLRMEM_SEL, SKIPMEMBIST, EN_EXT_CLK, and

EXT_CLK signals to all signal/pin tables and figures.

5396-DS108-R 06/25/07 Updated:

• “In-Band Management Port” on page 33.

• Table 28, “10/100/1000 Port Control Register (Page 00h: Address 00h–

0Fh),” on page 69

• Table 29, “IMP Port Control Register (Page 00h: Address 10h),” on page

69.

• Table 66, “Global Management Configuration Register (Page 02h:

Address 00h),” on page 86.

• Table 229, “Thermal Properties, With External Heat Sink, 23 mm. ´ 23 mm.

´ 15 mm. Blade Fin,” on page 180.

Removed:

• Memory Test Control Register (Page 00h: Address E0h) from page 75.

5396-DS107-R 07/12/06 Updated:

• Figure 39, ”256-Pin FBGA Package Outline Drawing,” on page 181.

3/6/2012 PJ87F

Revision HistoryBCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 4

5396-DS106-R 05/24/06 Added:

• Table 154, ”BER/CRC Error Counter Register (Page 10h ~ 1Fh: Address 2Eh

~ 2Fh),” on page 128.

• Table 155, ”PRBS Control Register (Page 10h ~ 1Fh: Address 30h ~ 31h),”

on page 128.

• Table 156, ”PRBS Control Register (Page 10h ~ 1Fh: Address 32h ~ 33h),”

on page 128.

• Table 157, ”Pattern Generator Control Register (Page 10h ~ 1Fh: Address

34h ~ 35h),” on page 129.

• Table 158, “Pattern Generator Control Register (Page 10h ~ 1Fh: Address

36h ~ 37h),” on page 130.

• Table 159, “Pattern Generator Control Register (Page 10h ~ 1Fh: Address

36h ~ 37h),” on page 130.

• Table 160, “Force Transmit 1 Register (Page 10h ~ 1Fh: Address 3Ah ~

3Bh),” on page 130.

• Table 161, “Block Address (Pages 10h–1Fh: Address 3Eh ~ 3Fh),” on page

131.

5396-DS105-R 04/19/06 Updated:

• Features list on front cover.

•“LED Interfaces” on page 50.

• Table 23, “Signal Descriptions,” on page 53.

• Table 24, “Pin Assignment (Listed by Pin Number),” on page 58.

• Table 25, “Pin Assignment (Listed by Signal Name),” on page 60.

• Figure 21, “Pins Top View,” on page 62.

• Table 27, “Control Registers (Page 00h),” on page 67.

• LED A, B, C, and D registers to Reserved in Table 27, “Control Registers

(Page 00h),” on page 67.

• Table 65, “Strap Value Register (Page 01h: Address 70h–73h),” on page

85.

• Table 94, “ARL Search Result Register 0 (Page 05h: Address 3Bh–3Eh),” on

page 98.

• Table 95, “ARL Search MAC/VID Result Register 1 (Page 05h: Address

40h–47h),” on page 98.

• Table 231, “Ordering Information,” on page 182.

Removed:

• LED A, B, C, and D register descriptions from section “Control Registers”

on page 67.

5396-DS104-R 11/10/05 Added:

• I-temp package ordering information to Table 223, “Ordering

Information”.

5396-DS103-R 09/21/05 Updated:

• The minimum, typical, and maximum for the 2.5V power rail pin in Table

208, “Electrical Characteristics”.

Revision Date Change Description

3/6/2012 PJ87F

Revision HistoryBCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch



February 07, 2012 • 5396-DS113-R Page 5

5396-DS102-R 09/16/05 Updated:

• The minimum, typical, maximum, and units for the 2.5V power rail pin in

Table 208, “Electrical Characteristics”.

Added:

• 3.3V power rail (IMP port) pin for IDD symbol in Table 208, “Electrical

Characteristics”8.

5396-DS101-R 09/13/05 Updated:

• Figure 16, “Serial EEPROM Connection,” on page 42.

• That the AUTO_POLL_DIS pin is pulled low, not high, during power-on/

reset in “MDC/MDIO Interface” on page 44.

• Figure 17, “MDC/MDIO Interface,” on page 44.

• When the switch is master-sourcing to When the switch is slave-driven in

“MDC/MDIO Interface Register Programming” on page 49.

• In Table 23, “Signal Descriptions,” on page 53:

– Description for HW_FWDG_EN.

–Type for EXTCLK.

• Pages 50h–60h to Reserved in Table 26, “Global Page Register Map,” on

page 64.

• The Description in Table 95, “ARL Search Control Register (Page 05h:

Address 30h),” on page 98.

• The Default in Table 169, “Queue N Weight Register (Page 30h: Address

81h–84h),” on page 132.

• Table 208, “Electrical Characteristics,” on page 158.

Added:

• Page 00 Addr 24H~25H Bit[10:8] to Table 19, “Serial LED Mode Matrix,”

on page 50.

Removed:

• From Table 7, “Behavior for Reserved Multicast Addresses,” on page 19:

– 01-80-C2-00-00-01

– 01-80-C2-00-00-10

5396-DS100-R 04/15/05 Initial release.

Revision Date Change Description

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