JEDEC Standard No.207
-i-
RADIO FRONT END–BASEBAND (RF-BB) INTERFACE
Contents
Foreword iii
Introduction ................................................................................................................................................................. iii
I.1 Data Path Overview.......................................................................................................................................... iii
I.2 Data Path Features ............................................................................................................................................ iii
I.3 Control Plane Overview.....................................................................................................................................iv
I.4 Control Plane Features.......................................................................................................................................iv
1 Scope ..................................................................................................................................................................1
2 References..........................................................................................................................................................2
3 Terminology ......................................................................................................................................................3
3.1 Terms and definitions .........................................................................................................................................3
3.2 Acronyms and abbreviations...............................................................................................................................4
3.3 Numeric representation.......................................................................................................................................4
4 Data path Functional layer ..............................................................................................................................5
4.1 Data path signals.................................................................................................................................................5
4.1.1 MCLK (Driven from RFIC to BBIC)....................................................................................................5
4.1.2 FCLK (Driven from BBIC to RFIC) .....................................................................................................5
4.1.3 TXNRX (Driven from BBIC to RFIC)..................................................................................................6
4.1.4 ENABLE (Driven from BBIC to RFIC)................................................................................................6
4.1.5 DIQ[11:10], DIQ[9:0] (Bidirectional) ...................................................................................................7
4.2 Data bus idle and turnaround periods .................................................................................................................7
4.3 Data path functional timing ................................................................................................................................8
4.3.1 Transmit burst........................................................................................................................................8
4.3.2 Receive burst .........................................................................................................................................9
4.3.3 Data path timing parameters..................................................................................................................9
5 Control Plane Functional layer......................................................................................................................11
5.1 Control Plane signals ........................................................................................................................................11
5.1.1 CPCLK (Driven from BBIC to RFIC).................................................................................................11
5.1.2 CPCSB (Driven from BBIC to RFIC) .................................................................................................11
5.1.3 CPMOSI, CPMISO and CPDIO..........................................................................................................12
5.2 Control plane functional timing........................................................................................................................13
5.2.1 Single transactions...............................................................................................................................13
5.2.2 Extended data transactions...................................................................................................................14
5.2.2 Extended data transactions (cont’d).....................................................................................................15
5.2.3 Control plane timing parameters..........................................................................................................15
5.3 Control plane clock frequency bands................................................................................................................16
6 Electrical layer ................................................................................................................................................17
6.1 Absolute maximum ratings...............................................................................................................................17
6.2 Normal operating conditions.............................................................................................................................17
6.3 DC characteristics.............................................................................................................................................17
6.4 AC characteristics.............................................................................................................................................18
6.5 Timing parameter measurement........................................................................................................................18
Annex A Data path applications and resulting sample/data/clock rates...............................................................19
A.1
Mandatory rates ................................................................................................................................................19
A.2 Optional rates....................................................................................................................................................20
Annex B Informative description of TXNRX and ENABLE burst control signalling ........................................21
B.1
Pulse synchronisation fault recovery ................................................................................................................22
Annex C Recommended PCB characteristics and component slew rates.............................................................23
Annex D Recommended component pin ordering..................................................................................................24
Standard Improvement Form
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