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《Intel架构》是Intel公司发布的一系列技术文档，主要针对Intel 64（也称为x86-64）和IA-32架构的软件开发者。这套文档由五卷组成，详细介绍了Intel处理器的硬件特性和软件开发所需的知识。本文将重点解析其中的第二卷，即《指令集参考，A-M》部分。卷二A主要涵盖了从A到M的指令集，这些指令是编程人员在编写汇编语言程序或理解底层计算机操作时需要掌握的关键元素。汇编语言（ASM）是与特定处理器紧密相关的低级编程语言，每个指令通常对应一个CPU硬件操作。 Intel 64和IA-32架构的指令集包括了各种功能的指令，例如数据处理、控制流转移、输入/输出操作等。例如，`MOV`指令用于在寄存器之间或寄存器与内存位置之间移动数据；`ADD`指令用于执行算术加法；`SUB`用于减法；`JMP`和`CALL`用于控制流程转移；`PUSH`和`POP`则涉及栈操作。这些基本指令是构建更复杂算法的基础。 Intel的指令集还包括了一些高级特性，如向量处理（如SSE、AVX家族），这些特性可以高效地处理大量数据，特别是在多媒体和科学计算领域。此外，还有对多线程支持的指令，如`MONITOR`和`MWAIT`，它们在实现硬件级别的并发控制时非常有用。文档中提到的“reserved”或“undefined”特征指的是那些尚未定义或者保留给未来使用的指令或功能。开发者不应依赖这些特性，因为Intel可能会在未来的处理器设计中对其作出改变，这可能导致兼容性问题或冲突。 Intel处理器可能存在设计缺陷或错误，即所谓的“errata”。这些错误可能会影响到处理器的性能或正确性。Intel会提供已知错误的最新清单，以帮助开发者规避这些问题。因此，在进行实际设计工作时，开发者需要定期检查最新的文档更新，确保代码的稳定性和兼容性。总体来说，《Intel Architecture Volume 2》是理解和开发Intel平台软件的重要参考资料，它为程序员提供了深入的硬件接口细节，帮助他们充分利用硬件资源，编写出高效且可靠的代码。同时，它还强调了安全性和可靠性，提醒开发者注意处理器可能出现的问题，并避免在关键应用中使用可能引发人身伤害或死亡的系统。

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Intel® 64 and IA-32 Architectures

Software Developer’s Manual

Volume 2A:

Instruction Set Reference, A-M

NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual

consists of five volumes: Basic Architecture, Order Number 253665;

Instruction Set Reference A-M, Order Number 253666; Instruction Set

Reference N-Z, Order Number 253667; System Programming Guide,

Part 1, Order Number 253668; System Programming Guide, Part 2,

Order Number 253669. Refer to all five volumes when evaluating your

design needs.

Order Number: 253666-037US

January 2011

ii Vol. 2A

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT-

ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH

PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR IN-

TENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUA-

TION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers

must not rely on the absence or characteristics of any features or instructions marked "reserved" or "unde-

fined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them. The information here is subject to change without no-

tice. Do not finalize a design with this information.

The Intel

64 architecture processors may contain design defects or errors known as errata. Current char-

acterized errata are available on request.

Intel

Hyper-Threading Technology requires a computer system with an Intel

processor supporting Hyper-

Threading Technology and an Intel

HT Technology enabled chipset, BIOS and operating system.

Performance will vary depending on the specific hardware and software you use. For more information, see

http://www.intel.com/technology/hyperthread/index.htm; including details on which processors support Intel HT

Technology.

Intel

Virtualization Technology requires a computer system with an enabled Intel

processor, BIOS, virtual

machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, perfor-

mance or other benefits will

vary depending on hardware and software configurations. Intel

Virtualization

Technology-enabled BIOS and VMM applications are currently in development.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, oper-

ating system, device drivers and applications enabled for Intel

64 architecture. Processors will not operate

(including 32-bit operation) without an Intel

64 architecture-enabled BIOS. Performance will vary de-

pending on your hardware and software configurations. Consult with your system vendor for more infor-

mation.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability

and a supporting operating system. Check with your PC manufacturer on whether your system delivers Ex-

ecute Disable Bit functionality.

Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo,

Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, Intel Atom, and VTune are trade-

marks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other coun-

tries.

*Other names and brands may be claimed as the property of others.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing

your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel

literature, may be obtained by calling 1-800-548-4725, or by visiting Intel’s website at http://www.intel.com

Vol. 2A iii

CONTENTS

PAGE

CHAPTER 1

ABOUT THIS MANUAL

1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . . 1-3

1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.1 Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.2 Reserved Bits and Software Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.3 Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.4 Hexadecimal and Binary Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.5 Segmented Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.7 A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

CHAPTER 2

INSTRUCTION FORMAT

2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND

VIRTUAL-8086 MODE 2-1

2.1.1 Instruction Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.2 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1.3 ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.4 Displacement and Immediate Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2 IA-32E MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.1 REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.1.1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.1.2 More on REX Prefix Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.1.3 Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.1.4 Direct Memory-Offset MOVs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.1.5 Immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.1.6 RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.1.7 Default 64-Bit Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.2.2 Additional Encodings for Control and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.3 INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.3.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.3.2 VEX and the LOCK prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.3.3 VEX and the 66H, F2H, and F3H prefixes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.3.4 VEX and the REX prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.3.5 The VEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.3.5.1 VEX Byte 0, bits[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3.5.2 VEX Byte 1, bit [7] - ‘R’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3.5.3 3-byte VEX byte 1, bit[6] - ‘X’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3.5.4 3-byte VEX byte 1, bit[5] - ‘B’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3.5.5 3-byte VEX byte 2, bit[7] - ‘W’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

CONTENTS

Vol. 2A

PAGE

2.3.5.6 2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or

dest Register Specifier2-21

2.3.6 Instruction Operand Encoding and VEX.vvvv, ModR/M. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.3.6.1 3-byte VEX byte 1, bits[4:0] - “m-mmmm” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.3.6.2 2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”. . . . . . . . . . . . . . . . . . 2-24

2.3.6.3 2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp” . . . . . . . . . . . 2-24

2.3.7 The Opcode Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.3.8 The MODRM, SIB, and Displacement Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.3.9 The Third Source Operand (Immediate Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.3.10 AVX Instructions and the Upper 128-bits of YMM registers . . . . . . . . . . . . . . . . . . . . . . 2-25

2.3.11 AVX Instruction Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.4 INSTRUCTION EXCEPTION SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.4.1 Exceptions Type 1 (Aligned memory reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.4.2 Exceptions . . . . . . . . . . . . . . . . . . . Type 2 (>=16 Byte Memory Reference, Unaligned)2-31

2.4.3 Exceptions Type 3 (<16 Byte memory argument). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.4.4 Exceptions Type 4 (>=16 Byte mem arg no alignment, no floating-point exceptions) .2-

2.4.5 Exceptions Type 5 (<16 Byte mem arg and no FP exceptions). . . . . . . . . . . . . . . . . . . . 2-34

2.4.6 Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues). . . . 2-35

2.4.7 Exceptions Type 7 (No FP exceptions, no memory arg). . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2.4.8 Exceptions Type 8 (AVX and no memory argument) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

2.4.9 Exception Type 9 (Intel AVX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

CHAPTER 3

INSTRUCTION SET REFERENCE, A-M

3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1.1 Opcode Column in the Instruction Summary Table (Instructions without VEX prefix) .

3-2

3.1.1.2 Opcode Column in the Instruction Summary Table (Instructions with VEX prefix) 3-4

3.1.1.3 Instruction Column in the Opcode Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.1.1.4 Operand Encoding Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . 3-9

3.1.1.5 64/32-bit Mode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . 3-10

3.1.1.6 CPUID Support Column in the Instruction Summary Table. . . . . . . . . . . . . . . . . . . . . . 3-11

3.1.1.7 Description Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.1.1.8 Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.1.1.9 Operation Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.1.1.10 Intel® C/C++ Compiler Intrinsics Equivalents Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.1.1.11 Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.1.1.12 FPU Flags Affected Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.1.1.13 Protected Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.1.1.14 Real-Address Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.1.1.15 Virtual-8086 Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.1.1.16 Floating-Point Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.1.1.17 SIMD Floating-Point Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.1.1.18 Compatibility Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.1.1.19 64-Bit Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Vol. 2A v

CONTENTS

PAGE

3.2 INSTRUCTIONS (A-M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

AAA—ASCII Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23

AAD—ASCII Adjust AX Before Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-25

AAM—ASCII Adjust AX After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27

AAS—ASCII Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-29

ADC—Add with Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31

ADD—Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35

ADDPD—Add Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . .3-38

ADDPS—Add Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . .3-40

ADDSD—Add Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . .3-42

ADDSS—Add Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . .3-44

ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

ADDSUBPS—Packed Single-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49

AESDEC—Perform One Round of an AES Decryption Flow. . . . . . . . . . . . . . . . . . . . . . . . .3-52

AESDECLAST—Perform Last Round of an AES Decryption Flow . . . . . . . . . . . . . . . . . . .3-54

AESENC—Perform One Round of an AES Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . .3-56

AESENCLAST—Perform Last Round of an AES Encryption Flow . . . . . . . . . . . . . . . . . . .3-58

AESIMC—Perform the AES InvMixColumn Transformation. . . . . . . . . . . . . . . . . . . . . . . . .3-60

AESKEYGENASSIST—AES Round Key Generation Assist. . . . . . . . . . . . . . . . . . . . . . . . . . .3-62

AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64

ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point Values . . .3-67

ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point Values . . . .3-69

ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values .

3-71

ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values 3-

ARPL—Adjust RPL Field of Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

BLENDPD — Blend Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . .3-78

BLENDPS — Blend Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . .3-80

BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values. . . . . . .3-83

BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values. . . . . . . .3-86

BOUND—Check Array Index Against Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-89

VBROADCAST—Load with Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-92

BSF—Bit Scan Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-96

BSR—Bit Scan Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-99

BSWAP—Byte Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102

BT—Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104

BTC—Bit Test and Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107

BTR—Bit Test and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110

BTS—Bit Test and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113

CALL—Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-116

CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Dou-

bleword to Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135

CLC—Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-137

CLD—Clear Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-138

CLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139

CLI — Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-141

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