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### 嵌入式计算机视觉与智能摄像机 #### 概述嵌入式计算机视觉技术结合了嵌入式系统与计算机视觉领域的专业知识，旨在通过集成高性能计算单元于小型、低功耗设备中来实现复杂视觉任务的处理。随着硬件性能的不断提升以及集成电路技术的进步，嵌入式计算机视觉已成为工业、军事及消费市场中不可或缺的技术之一。 #### 计算机视觉的基本概念计算机视觉（Computer Vision, CV）是指让计算机能够理解和解释图像或视频信息的技术。该技术主要包括以下几个关键步骤： 1. **图像获取**：通过摄像头或其他传感器捕捉图像。 2. **图像预处理**：对原始图像进行滤波、灰度转换等操作以减少噪声并增强图像特征。 3. **特征提取**：从预处理后的图像中提取有用的信息，如边缘、角点等。 4. **图像理解**：基于提取的特征识别物体、场景或行为。 5. **决策与行动**：根据图像理解的结果做出相应的决策或执行特定的操作。 #### 嵌入式系统的定义与特点嵌入式系统是一种专用计算机系统，它由数字和可能的模拟电路组成，具有明确的目的。其硬件和软件都针对特定功能进行了优化，以实现更短的启动时间、更高的处理速度、更大的可靠性、更低的成本、更低的功耗等特性。这些系统通常包含一个或多个处理器，以及相关的内存芯片、输入/输出控制器、协处理器和其他电子组件。 #### 嵌入式计算机视觉的挑战与技术在嵌入式环境中实施计算机视觉面临着独特的挑战，尤其是在资源有限的情况下如何高效地执行复杂的算法。以下是一些关键技术点： 1. **硬件选择**：根据应用场景选择合适的硬件平台至关重要。例如，使用数字信号处理器（DSP）、现场可编程门阵列（FPGA）或嵌入式平台可以显著提高处理速度。 2. **算法优化**：为了适应有限的资源，需要对传统计算机视觉算法进行优化，包括但不限于简化算法结构、采用近似算法等。 3. **并行计算**：利用多核处理器或GPU进行并行处理可以有效提升处理速度。 4. **能耗管理**：在移动设备和远程监控等应用中，能耗管理是至关重要的考虑因素。 #### 智能摄像机的应用实例智能摄像机是嵌入式计算机视觉的一个典型应用案例，它们不仅具备捕捉图像的功能，还能通过内置的处理单元对图像数据进行实时分析。智能摄像机广泛应用于： 1. **安全监控**：通过人脸识别、行为分析等功能实现智能监控。 2. **智能家居**：集成到智能家居系统中，实现家庭自动化控制。 3. **自动驾驶**：作为车辆感知系统的一部分，用于识别交通标志、行人等。 4. **零售分析**：通过分析顾客行为提供商业洞察。 #### 总结嵌入式计算机视觉与智能摄像机代表了计算机视觉技术向实际应用领域迈出的重要一步。通过不断的技术创新和优化，这些技术正在改变我们的生活方式，并将在未来继续发挥重要作用。随着更多高性能且低功耗的硬件平台的出现，嵌入式计算机视觉的应用前景将更加广阔。

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Embedded Computer Vision and Smart Cameras

Mathias K

olsch

Department of Computer Science,

Naval Postgraduate School, Monterey, CA

Branislav Kisa

canin

Delphi Corporation

1 Abstract

This paper accompanies the tutorial on Embedded Computer Vision and Smart Cameras, held at Embed-

ded Systems Conference Silicon Valley 2007. The tutorial provides practitioners in the embedded systems

community with an insight into computer vision challenges and techniques. It discusses algorithmic and

hardware-speciﬁc considerations when “outsourcing” computation to a DSP, FPGA, or onto an embedded

platform, and provides guidelines for how to best improve the runtime performance of computer vision ap-

plications.

Embedded computers and computer vision systems are two of the largest growths markets in the industry.

They take full advantage of Moore’s Law of shrinking form factors and increasing integration density and

computational power. “Systems on a chip” enjoy growing popularity because of the power-, cost-, and space-

saving combination of previously external chips onto the same die, including analog-to-digital converters,

bus interfaces, I/O controllers, and even analog components. With the help of these integrated processing

capabilities, computer vision has become a viable and preferable solution to many legacy and novel problem

settings in industry, military, and consumer markets.

2 Introduction

To avoid confusion and misunderstandings, a couple deﬁnitions are in order.

An embedded computer is a set of digital and possibly analog circuitry that has a precisely deﬁned pur-

pose. It comprises one or multiple processors that serve a dedicated purpose for one particular system.

Its hardware and software are optimized for a particular function to achieve shorter startup times, higher

processing speed, greater reliability, lower cost, lower power consumption and/or some other property that

a general-purpose computing system does not fulﬁll. The software is often called ﬁrmware, emphasizing its

inseparability from the hardware. At the core of an embedded system is a microprocessor, usually surrounded

by memory chips, input/output controllers, co-processors, analog components, and any imaginable electronic

component. Chips for embedded systems often have a wider temperature operating range (say, -45C to 85C

as opposed to 0C to 45C (todo check) for general-purpose CPUs. All this is embedded in the device that it

controls or monitors, often creating a necessary mutual dependency.

Embedded computers are particularly well suited to process streams of data at high speeds with relatively

small software programs, such as video processing in television sets and DVD players, real-time control tasks

in cars and airplanes, and cell phone signal processing, but also in microwave ovens, digital parking meters

and pace makers. Dedicated buses can be used to avoid competing with other processing needs. Other than

on CPUs, data can be processed in a highly parallel fashion, with blazing speeds, and without interfering with

other CPU tasks.

A smart camera is a combination of an imaging device and a computational unit whose combined output

is a processed video stream or some higher-level information (such as the location and identity of a person),

but not the original video stream. At a sufﬁciently high abstraction level, even a PC with attached web

cam can serve as a smart camera. However, integration and miniaturization make it increasingly feasible to

develop smart cameras with much smaller form factors, down to single-chip devices that integrate processing

power right on the imaging chip (usually a CMOS chip).

The term “smart camera” is not used consistently as deﬁned above, and the amount of video processing

can vary a lot from device to device. The line between what qualiﬁes as a smart camera is blurry. For example,

pixel-wise transformations (such as with a lookup-table (LUT) are generally not regarded as complex enough

to count as smart cameras. On the other hand, if the device can execute rather arbitrary code, it should be

considered “smart.”

2.1 Related Publications

In addition to resources cited throughout this document, the reader might be interested in the following papers,

journals, and internet resources.

Springer’s Journal of Real-Time Image Processing (JRTIP), the International Symposium on System-

on-Chip (until 2002: System-on-Chip Seminar)

, the International Workshop System-on-Chip for Real-

Time Applications

, the workshop on Embedded Computer Vision (ECV06) at CVPR 2006, and the IEEE

Symposium on Field-Programmable Custom Computing Machines (IEEE FCCM). Individual contributions

are Bernhard Rinner’s SmartCam

, Bramberger et al.’s work [5], Wolf et al.’s work [58], Edwards et al.’s

work [14], Randy Allen’s article on converting ﬂoating-point applications to ﬁxed-point

, and Joe Lemieux’

article on Fixed-point math in C

3 Hardware

We brieﬂy describe the main characteristics of various hardware in the following sections, from rather

general-purpose to system-speciﬁc chips.

3.1 Digital Signal Processors

A digital signal processor, or DSP, is similar to a general-purpose processor (GPP) in many aspects. It has

ﬁxed logic, that is, the connections between logic gates can not be changed. It provides a ﬁxed instruction

set (ISA) to the programmer, and it expects a program in this ISA which it will then execute in a sequential

manner (as opposed to dataﬂow). Most DSP ISAs exhibit a similar structure as GPP ISAs, complete with

arithmetic and logic instructions, memory access, registers, control ﬂow and what have you.

Distinguishing it from general-purpose CPUs, a DSP’s instruction set is optimized for matrix operations,

particularly multiplication and accumulation (MAC), traditionally in ﬁxed-point arithmetic, but increasing

also for double-precision ﬂoating point arithmetic. DSPs exhibit deep pipelining and thus expect a very

linear program ﬂow without frequent conditional jumps. They provide for SIMD instructions, assuming a

http://www.cs.tut.ﬁ/soc/

http://www.socrt.org/IWSOC2005/

http://www.iti.tugraz.at/en/research/smartcam/smartcam.html

http://www.embedded.com/showArticle.jhtml?articleID=47903200

http://www.embedded.com/showArticle.jhtml?articleID=15201575

large amount of data that has to be processed by the same, relatively simple, mathematical program. SIMD

programs exploit instruction-level parallelism, but necessitate the exact same instruction for the multiple data.

VLIW relaxes this constraint in that it allows different instructions (opcodes) to be packed together in a Very

Long Instruction Word, and every instruction therein processes a different datum concurrently. Many DSPs

are VLIW architectures. The types of instructions that are allowed together within one VLIW (and thus will

be executed in parallel) depends on the function units that can operate in parallel. For example, if a DSP has

two ﬁxed-point MAC units and two ﬂoating-point MAC units, then at most two ﬁxed-point MAC operations

can be placed into the same VLIW. This constraint is relaxed even further in so-called MIMD machines,

where multiple identical processors can independently execute arbitrary instructions on non-dependent data.

You might note that modern CPUs and their multiple-dispatch pipelines do exactly that – schedule multi-

ple instructions concurrently. With DSPs, however, there is no such intelligent pipeline. Instead, the burden

of scheduling is on the compiler: it has to co-schedule instructions for independent data operations and opti-

mize the packing of instructions in width (for example, four instructions per word) and in sequence (control

ﬂow). DSPs do not perform such complex CPU operations as branch prediction or instruction reordering.

Here, too, the compiler has to perform the optimizations.

DSP programs are relatively small programs (tens or hundreds of LOC), with few branch and control

instructions, as opposed to entire operating systems running on general purpose CPUs. Frequently, a single,

tight, and heavily optimized loop is executed once for every data element or set thereof.

Since DSPs usually execute small programs on huge amounts or endless streams of data, these two pieces

of information are stored in separate memory blocks, often accessible through separate buses. This is called

a Harvard architecture, as opposed to the GPP’s von Neumann architecture, in which both program and data

are stored in the same memory. Since the program does not change (ﬁrmware!), many DSPs provide on-

chip ROM (typically in the order of 10kB) for program storage, and a small but efﬁcient RAM hierarchy for

data storage. Frequently, an embedded system also includes a separate non-volatile memory chip such as an

EEPROM or ﬂash memory.

DSPs lack just a few operations, mostly operating-speciﬁc instructions. Otherwise, the can do the same

as CPUs, but they can perform them faster, they need less power, they dissipate less heat, they have short

start-up times, they can operate in a larger temperature range, and they are less expensive because the chip

contains only the necessary components.

Manufacturers of DSPs include Agere Systems, Analog Devices, Inﬁneon, Lucent Technologies, Mo-

torola (Freescale Semiconductor), Philips Electronics, Texas Instruments, and Zilog. Bruno Paillard wrote

a good introduction to DSPs, it can be found at http://www.softdb.com/media/DSP

Introduction en.pdf. A

textbook resource by Wiley is Lynn and Fuerst’s “Introductory Digital Signal Processing with Computer

Applications. The USENET group comp.dsp might also be of interest to the reader.

3.2 Field Programmable Gate Arrays

A Field Programmable Gate Array, or FPGA, is a semiconductor in which the actual logic can be modi-

ﬁed to the application builder’s needs. The chip is a relativley inexpensive, off-the-shelf device that can be

programmed in the “ﬁeld” and not the semiconductor fab. It is important to note the difference in software

programming and logic programming, or logic design as it is usually called: a software program always

needs to run on some microcontroller with an appropriate instruction set architecture (ISA), whereas a logic

program is the microcontroller. In fact, this logic program can specify a controller that accepts as input a

particular ISA, for example, the ISA of an ARM CPU, effectively turning the FPGA into an ARM CPU.

This is a so-called soft core, built from general-purpose logic blocks. These soft cores, or better the

right to use the intellectual property, can be purchased from companies such as Xilinx and Altera. They

are then “downloaded” to the FPGA where they implement the desired functionality. Some of the modern

FPGAs integrate platform- or hard multi-purpose processors on the logic such as a PowerPC, ARM, or a DSP

architecture. case of an Atmel FPSLIC. Other common hard and soft modules include multipliers, interface

logic, and memory blocks. Some more complex FPGAs can modify and reprogram their general-purpose

logic blocks even on the ﬂy, that is, while another part of the chip keeps running.

The logic design determines the FPGA’s functionality. This conﬁguration is written to the device and

is retained until it is erased. To be precise, there are three types of FGPAs: antifuse, SRAM, and FLASH.

Antifuse chips are not re-programmable. FLASH (EPROM) is also non-volatile, meaning that the logic

design stays on the chip through power cycles. It can be erased and re-programmed many times. SRAM

programming on the other hand is volatile – it has to be programmed at power on.

The huge beneﬁt of an FPGA is the great deal of ﬂexibility in logic. One can, for example, create 320

parallel accumulation buffers and ALUs, summing up an entire 320x240 image in 240 clock cycles. They

can achieve speeds close to DSPs and ASICs, require a bit more power than an ASIC, have much lower

non-recurring engineering (NRE) costs, but higher volume prices than ASICs.

One of the main difﬁculties for developing embedded systems with FPGAs is the unfamiliarity with

the programming model: everything is possible, and in many different ways. One of the ﬁrst difﬁculties

is deviding the responsibilities between the FPGA and a GPP, and between the FPGA’s core CPU and into

possible other chips on the platform.

FPGA manufacturers include Achronix Semiconductor, Actel, Altera, AMI Semiconductor, Atmel, Cy-

press Semiconductor, Lattice Semiconductor, QuickLogic, and Xilinx. An introduction to FPGAs can be

found at http://www.tutorial-reports.com/computer-science/fpga/tutorial.php.

3.3 Application-Speciﬁc Integrated Circuits

An Application-Speciﬁc Integrated Circuit (ASIC) is a chip that is designed and optimized for one particular

application. The logic is customized to include only those components that are necessary to perform its task.

Even though modules are reused from ASIC to ASIC just like FPGA modules, a large amount of design

and implementation work goes into every ASIC. Their long production cycle, their immensely high one-time

cost, and their limited beneﬁts in speed gains put them slightly out of scope of this tutorial. Contributing to

the high cost, they need to be respun if the design changes just slightly, costing months and usually hundreds

of thousands of dollars.

Their beneﬁts lie potential power savings and a decreasing asymptotic cost (with high unit numbers). A

structured ASIC is a type of ASIC that offers the same beneﬁts (power, speed, unit cost) as ASICs, but the

NRE costs are typically lower than for ASICs, sometimes only 25% as high. Companies offering ASICs

and structured ASIC processes are AMI Semiconductor, Fujitsu, LSI Logic, and NEC. Altera’s “HardCopy”

method attempts to achieve the same beneﬁts as structured ASICS.

3.4 System on Chip

A System on Chip (SoC) contains all essential components of an embedded system on a single chip. The

deﬁnition is blurry, as sometimes this only refers to the digital components and sometimes it includes analog

components. DSPs have an increasing amount of peripherals included on the die as well, warranting the

inclusion in this category. Most SoCs have a GPP such as an ARM, MIPS, PowerPC, or an x86-based core

at their heart, supplemented by a DSP. What makes these chips an entire system are the inclusion of a bewil-

dering array of peripherals. In addition to standard microcontroller components (busses, clocks, memory),

typical integrated components are:

• Ethernet MAC

• PCMCIA

• USB 1.0 and 2.0 controller

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