基于IAR的STM8L152的USART+ADC(双通道)带DMA+RTC定时唤醒+外部中断唤醒+低功耗HALT模式（源码）

/** ****************************************************************************** * @file stm8l15x_tim1.c * @author MCD Application Team * @version V1.4.0 * @date 09/24/2010 * @brief This file provides all the TIM1 firmware functions. ****************************************************************************** * @copy * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2> */ /* Includes ------------------------------------------------------------------*/ #include "stm8l15x_tim1.h" /** @addtogroup STM8L15x_StdPeriph_Driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter); static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter); static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter); static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter); /** * @addtogroup TIM1_Public_Functions * @{ */ /** * @brief Deinitializes the TIM1 peripheral registers to their default reset values. * @param None * @retval None */ void TIM1_DeInit(void) { TIM1->CR1 = TIM1_CR1_RESET_VALUE; TIM1->CR2 = TIM1_CR2_RESET_VALUE; TIM1->SMCR = TIM1_SMCR_RESET_VALUE; TIM1->ETR = TIM1_ETR_RESET_VALUE; TIM1->IER = TIM1_IER_RESET_VALUE; /* Disable channels */ TIM1->CCER1 = TIM1_CCER1_RESET_VALUE; TIM1->CCER2 = TIM1_CCER2_RESET_VALUE; /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */ TIM1->CCMR1 = 0x01; TIM1->CCMR2 = 0x01; TIM1->CCMR3 = 0x01; TIM1->CCMR4 = 0x01; /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */ TIM1->CCER1 = TIM1_CCER1_RESET_VALUE; TIM1->CCER2 = TIM1_CCER2_RESET_VALUE; TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE; TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE; TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE; TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE; TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE; TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE; TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE; TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE; TIM1->ARRH = TIM1_ARRH_RESET_VALUE; TIM1->ARRL = TIM1_ARRL_RESET_VALUE; TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE; TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE; TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE; TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE; TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE; TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE; TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE; TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE; TIM1->OISR = TIM1_OISR_RESET_VALUE; TIM1->EGR = 0x01; /* TIM1_EGR_UG */ TIM1->DTR = TIM1_DTR_RESET_VALUE; TIM1->BKR = TIM1_BKR_RESET_VALUE; TIM1->RCR = TIM1_RCR_RESET_VALUE; TIM1->SR1 = TIM1_SR1_RESET_VALUE; TIM1->SR2 = TIM1_SR2_RESET_VALUE; } /** * @brief Initializes the TIM1 Time Base Unit according to the specified parameters. * @param TIM1_Prescaler specifies the Prescaler value. * @param TIM1_CounterMode specifies the counter mode from * @ref TIM1_CounterMode_TypeDef . * @param TIM1_Period specifies the Period value. * @param TIM1_RepetitionCounter specifies the Repetition counter value * @retval None */ void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler, TIM1_CounterMode_TypeDef TIM1_CounterMode, uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter) { /* Check parameters */ assert_param(IS_TIM1_COUNTER_MODE(TIM1_CounterMode)); /* Set the Autoreload value */ TIM1->ARRH = (uint8_t)(TIM1_Period >> 8); TIM1->ARRL = (uint8_t)(TIM1_Period); /* Set the Prescaler value */ TIM1->PSCRH = (uint8_t)(TIM1_Prescaler >> 8); TIM1->PSCRL = (uint8_t)(TIM1_Prescaler); /* Select the Counter Mode */ TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)(~(TIM1_CR1_CMS | TIM1_CR1_DIR))) | (uint8_t)(TIM1_CounterMode)); /* Set the Repetition Counter value */ TIM1->RCR = TIM1_RepetitionCounter; } /** * @brief Initializes the TIM1 Channel1 according to the specified parameters. * @param TIM1_OCMode specifies the Output Compare mode from * @ref TIM1_OCMode_TypeDef. * @param TIM1_OutputState specifies the Output State from * @ref TIM1_OutputState_TypeDef. * @param TIM1_OutputNState specifies the Complementary Output State from * @ref TIM1_OutputNState_TypeDef. * @param TIM1_Pulse specifies the Pulse width value. * @param TIM1_OCPolarity specifies the Output Compare Polarity from * @ref TIM1_OCPolarity_TypeDef. * @param TIM1_OCNPolarity specifies the Complementary Output Compare * Polarity from @ref TIM1_OCNPolarity_TypeDef. * @param TIM1_OCIdleState specifies the Output Compare Idle State from * @ref TIM1_OCIdleState_TypeDef. * @param TIM1_OCNIdleState specifies the Complementary Output Compare * Idle State from @ref TIM1_OCIdleState_TypeDef. * @retval None */ void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode, TIM1_OutputState_TypeDef TIM1_OutputState, TIM1_OutputNState_TypeDef TIM1_OutputNState, uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, TIM1_OCIdleState_TypeDef TIM1_OCIdleState, TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState) { /* Check the parameters */ assert_param(IS_TIM1_OC_MODE(TIM1_OCMode)); assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState)); assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState)); assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity)); assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState)); assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState)); /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output N State, the Output Polarity & the Output N Polarity*/ TIM1->CCER1 &= (uint8_t)(~(TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP)); /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */ TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC1E) | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC1NE)) | (uint8_t)( (uint8_t)(TIM1_OCPolarity & TIM1_CCER1_CC1P) | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC1NP))); /* Reset the Output Compare Bits & Set the Ouput Compare Mode */ TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode); /* Reset the Output Idle state & the Outp