RISC处理器的实现
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2009-11-18
10:59:07
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7941927embedded_risc.tar.gz （65个子文件） 
embedded_risc CVS 
Entries 132B Repository 14B Root 14B Verilog ALU.V 4KB uart.v 6KB sdram_cntrl.v 2KB data_in_reg.v 1KB command_if.v 3KB soc.v 11KB instruction_cache_way0.v 3KB data_cache_way0.v 3KB CONTROL.V 18KB MUX12.V 890B cmd_detector.v 6KB dma_fifo.v 2KB data_cache_way1.v 3KB CVS Entries 2KB Repository 22B Root 14B ACC.V 2KB dma_cntrl.v 7KB MEM.V 2KB data_port.v 3KB lru_data_cache.v 8KB dma_internal_reg.v 7KB instruction_cache_way1.v 3KB ras_cas_delay.v 2KB sdram.v 47KB sdram_port.v 1KB IR.V 2KB parameter.v 3KB sdramctrl_rtl.v 4KB bus_arbiter.v 8KB cmd_ack.v 1KB timer.v 5KB cmd_decoder.v 3KB ref_timer.v 1KB instruction_cache_way2.v 3KB data_cache_way3.v 3KB MUX16.V 928B data_cache_way2.v 3KB lru_instruction_cache.v 9KB instruction_cache_way3.v 3KB ref_ack.v 2KB sdram_mux.v 845B fsm.v 5KB cmd_internal_reg.v 2KB oe_generator.v 4KB cmd_generator.v 6KB k9f1g08u0m.v 44KB PC.V 1KB risc.v 8KB flash_ctrl.v 4KB embedded_risc CVS Entries 2B Repository 28B Root 14B
SOC_Design.pdf 69KB Machine_Language 
program.txt 7KB CVS Entries 46B Repository 31B Root 14B Test_Bench_Verilog CVS Entries 50B Repository 33B Root 14B Top_level_tb.tf 5KB资源评论
尘恩cj2014-05-17有注释，还可以。
