BCM5345M交换机控制芯片资料资源-CSDN文库

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### BCM5345M交换机控制芯片知识点详解 #### 一、概述 BCM5345M是一款高性能的24-Gigabit交换处理器芯片，适用于多种网络应用场景，包括工作组交换机、桌面交换机以及数据中心交换机等。该芯片支持所有端口在全速线速模式下工作，提供卓越的数据传输性能。 #### 二、特性与功能 ##### 1. 高速端口支持 - **24个千兆端口**：BCM5345M支持24个千兆端口，在单个设备中实现高速数据交换。 - **RGMII接口**：这些端口采用RGMII（Reduced Gigabit Management Independent Interface）标准，支持802.3ab (1000BASE-T) 接口标准，适用于各种物理层设备。 ##### 2. 多层转发能力 - **L2 MAC地址查找**：芯片内置8K条目MAC地址表，能够高效处理基于L2 MAC地址的帧转发。 - **巨帧支持**：支持最大9216字节的巨帧转发，提高大流量数据包的传输效率。 - **VLAN支持**：支持高达4K个VLAN地址，增强网络安全性和隔离性。 - **优先级队列**：支持基于802.1p用户优先级位或TOS字段的四级别优先级队列，优化不同服务类型的传输质量。 ##### 3. 流量控制与管理 - **流控与聚合**：支持IEEE 802.3x标准的全双工流控机制及背压机制，确保稳定的数据传输。 - **端口汇聚**：支持802.3ad链路汇聚控制协议(LACP)，通过端口汇聚提高带宽利用率。 - **速率控制**：支持对各个端口进行速率控制，防止过载。 - **缓冲管理**：内置512-KB的包缓存，具有高级缓冲管理和错误校正代码(ECC)，保证数据传输的准确性和可靠性。 ##### 4. 协议支持 - **生成树协议**：支持802.1s生成树协议，实现快速收敛和环路避免。 - **多播组支持**：最多可支持256个IP多播组，并可以选择跨VLAN边界传输。 - **远程监控支持**：支持RMON和SMON中的选定MIB组，方便网络管理和监控。 ##### 5. 集成PCI接口 - **PCI接口**：内置PCI接口，用于连接主机系统，支持全功能管理应用。 ##### 6. 其他特性 - **高级配置与监控机制**：提供所有必要的计数器和帧捕获机制，便于高级配置和故障诊断。 #### 三、应用场景 - **工作组交换机**：适用于小型办公室或工作组内部的数据交换。 - **桌面交换机**：满足个人电脑或工作站之间的高速连接需求。 - **数据中心交换机**：适用于数据中心内的高速网络架构，支持高密度的端口连接。 #### 四、总结 BCM5345M是一款高度集成的24-Gigabit交换机控制芯片，通过其丰富的功能特性和高性能设计，能够在多种网络环境中提供稳定、高效的交换服务。无论是工作组级别的小型网络还是大型数据中心，BCM5345M都能够满足用户的多样化需求，成为构建高效网络基础设施的关键组件之一。

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3/23/2006 VRWTC

Data Sheet

BCM5345M-DS05

5345M-DS05-R

16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 03/14/06

24-Gigabit Switching Processor

Figure 1: Functional Block Diagram

ENERAL DESCRIPTION

EATURES

The BCM5345M-DS05 switching processor chip

supports 24-Gigabit ports in a single device with all

ports in wirespeed operation. The BCM5345M-DS05 is

ideal for applications such as Gigabit Ethernet (GbE)

workgroup switches, desktop switches, and data center

switches. It supports 24 ports of Reduced Gigabit

Management Independent Interface (RGMII) (802.3ab,

1000BASE-T), and interfaces with full-duplex operation

at Gigabit speed and full-duplex or half-duplex

operation at 10/100 Mbps speed (using 10BASE-T/

100BASE-T). By using the chip’s trunking feature, the

BCM5345M-DS05 can support a higher port count

(such as 48 ports).

The BCM5345M-DS05 forwards Ethernet frames with

lengths between 64 bytes to 9 KB, based on L2 MAC

address lookups in the 8K entry on-chip MAC address

table. The device supports four levels of priority that can

be assigned either from the 802.1p user priority bits or

the TOS field for Differentiated Services. The device

also supports flow control as well as port trunking

(802.3ad). In addition, individual ports can be rate-

controlled. The BCM5345M-DS05 device offers an

integrated Peripheral Component Interconnect (PCI)

interface to support fully-managed applications. All the

required counters and frame trapping mechanisms are

incorporated into the device.

• Supports 24 Gigabit ports in wirespeed operation

• 24 Gigabit ports support RGMII interfaces

• On-chip L2 search table supports 8K MAC addresses

• Jumbo frame supports up to 9216 bytes

• Supports 4K VLAN address

• 802.1s Spanning Tree protocol

• Supports rapid spanning tree

• Supports 802.1p and/or DiffServ with four priority

queues

• Supports 802.3ad Link Aggregation Control Protocol

(LACP)

• Supports selected MIB groups in RMON and SMON

• Supports up to 256 IP multicast groups with the option

to cross VLAN boundaries

• Full-duplex and half-duplex operation with IEEE

802.3x flow control and backpressure

• On-chip 512-KB packet memory with sophisticated

buffer management and ECC (Error Correction Code)

• Offers per-port rate control

• Supports 802.1x access control protocol

• GMII port for remote management Interface

• Packaged in 676-pin BGA

• Extremely low-power consumption (4.5W)

Shared Buffer

Output

Queueing

Buffer

Manager

MIB

Counters

PCI

Interface

Serial

Parallel

Serial

Tx FIFO

Rx FIFO

Table

Management

L2 MAC

Table

VLAN Table

Tx FIFO

Rx FIFO

G MAC

Tx FIFO

Rx FIFO

Tx FIFO

Rx FIFO

G MAC G MAC

Port

Manager

RGMII

Interface

RGMII

Interface

RGMII

Interface

To CP

3/23/2006 VRWTC

Data Sheet BCM5345M-DS05

03/14/06

Broadcom Corporation

Document 5345M-DS05-R Page iii

5345M-DS02-R 11/24/04 Updated:

• “Functional Block Diagram”

• “Overview”

• “Pin Diagram (Top View)” figure

• “Gigabit Interface” table

• “CPU Interface” table

• “Voltage Ground“ table

• “Full-Duplex Flow Control (802.3X)”

• “Layer 2 Switching”

• “Multicast Frames”

• “Buffer Management”

• “EEPROM Interface”

• “Reprogramming the EEPROM Configuration”

• “Clause 22 MDIO Frame Format and Non-IEEE Registers” figure

• “Accessing the G-PHY Via MDIO” figure

• “Theory of Operation”

• “Light Management Control” figure

• “Light Management Timing” figure

• “Remote Management Interface”

• “Table Data Buffer for Table Command Register” to “Table Data Buffer/DMA

Channel Address for Table Command Register”

• “Device Information Register (Register 0x11)” table

• “Management Setup Register (Register 0x17)“ table

• “Management Port Destination MAC Address Register 1–3”

• “Age Timer Register (Register 0x1E)” table

• “Trunking Assignment Setup Register 1–6”

• “Output Queue Management Register 1–2 (Register 0x71~0x72)” table

• “Output Queue Management Register 3–4 (Register 0x73~0x74)” table

• “Output Queue Management Register 5–6 (Register 0x75~0x76)” table

• “Output Queue Management Register 7–8 (Register 0x77~0x78)” table

• “Global GbE Port Control Register 2 (Register 0x81)” table

• “Vendor-Specific PHY Configuration Register”

• “1000BASE-T 10/100 MAC Configuration Register (Register 0x8C)” table

• “Customer BPDU Registers”

• “Station MAC Address Register”

• “Test Control Register 1 (Register 0x98)” table

• “Test Control Register 2 (Register 0x99)” table

• “Port Configuration Register 1 (Register 1-xxxxx-000)” table

• “Port Configuration Register 4 (Register 1-xxxxx-011)” table

• “Port Configuration Register 5 (Register 1-xxxxx-100)” table

5345M-DS02-R

(Cont.)

11/24/04 • “Port Status Register 1–2”

• “RGMII Timing” table

• “DC Electrical Characteristics” table”

Added:

• “CPU Interrupt Vector Mask Register”

Revision Date Description

3/23/2006 VRWTC

Broadcom

, the pulse logo, Connecting everything

, and the Connecting everything logo are among the trademarks of

Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks

or trade names mentioned are the property of their respective owners.

This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or

certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous

substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS", WITHOUT

WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING,

WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, AND NON-INFRINGEMENT.

Broadcom Corporation

P.O. Box 57013

16215 Alton Parkway

Irvine, CA 92619-7013

Printed in the U.S.A.

5345M-DS01-R 10/21/03 Updated:

• “Gigabit Interface” table

• “CPU Interface” table

• “Ethernet Frame Format”

• “Pin Diagram (Top View)” figure

• “Voltage Ground” table

• “Full-Duplex Flow Control (802.3X)”

• “Port State”

• “Priority Queuing”

• “Link Aggregation”

• “Buffer Management”

• “Trunking Assignment Setup Register 1–6” and “Trunking Assignment Setup

Registers (Register 0x1F ~ 0x24)” table

• “Port VLAN Map Registers (36 Registers, Three Registers for Two Ports)” table

• “Output Queue Maxlimit Registers for GbE Port” table

• “Output Queue Maxlimit Registers for CPU Port” table

• “Port Configuration Register 3 for1000BASE-T (Register 1-xxxxx-010)” table

• “Electrical Specifications”

• “DC Electrical Characteristics” table

• “Power-Up Sequence” figure

Added:

• “EEPROM to Register Mapping” figure

• “MIB Access Address Format” figure

• “MIB Counter” table

Removed:

• “MIB Counter Rx Statistics”

• “MIB Counter Tx Statistics”

• “MIB Counter Flow/Security Control Statistics”

• “Management Information Base Counters”

• “Management Information Base Counters (a)” figure

• “Management Information Base Counters (b)” figure

5345M-DS00-R 09/11/03 Initial release.

Revision Date Description

3/23/2006 VRWTC

Data Sheet BCM5345M-DS05

03/14/06

Broadcom Corporation

Document 5345M-DS05-R Page ix

TABLE OF CONTENTS

Section 1: Overview.............................................................................................................1

Section 2: Pin Description ..................................................................................................7

Section 3: Functional Description....................................................................................21

Ethernet Frame Format.............................................................................................................................. 21

Reduced Gigabit Media Interface ............................................................................................................. 21

Flow Control ............................................................................................................................................... 22

Full-Duplex Flow Control (802.3x)......................................................................................................... 22

Half-Duplex Flow Control (Backpressure)............................................................................................. 22

Layer 2 Switching....................................................................................................................................... 23

Port State.............................................................................................................................................. 23

Hardware Aging .................................................................................................................................... 24

Example 1: Deleting all Entries with Port = 4................................................................................. 25

Example 2: Deleting all Entries with Port = 4 in VLAN ID = 2........................................................ 25

Special Frame Identification and Trapping ........................................................................................... 26

L2 Address, Multicast, VLAN, and Multiple-Spanning-Tree VLAN Tables............................................ 27

Unicast Frames..................................................................................................................................... 32

Multicast Frames................................................................................................................................... 58

Priority Queuing .................................................................................................................................... 58

Link Aggregation........................................................................................................................................ 59

Broadcast Storm Control and Rate Control............................................................................................. 62

Port Monitoring .......................................................................................................................................... 62

Buffer Management.................................................................................................................................... 63

EEPROM Interface...................................................................................................................................... 65

Start and Stop Bit.................................................................................................................................. 67

Write Cycle Timing................................................................................................................................ 67

Read Cycle Timing................................................................................................................................ 68

Reprogramming the EEPROM Configuration.......................................................................................... 70

Accessing Registers Via MDC/MDIO Management Interface................................................................. 72

Light Management Interface ..................................................................................................................... 74

Theory of Operation .............................................................................................................................. 76

Light Management Pin List ................................................................................................................... 79