存储FTL Super块论文
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A Superblock-based Flash Translation Layer for NAND
Flash Memory
∗
Jeong-Uk Kang Heeseung Jo Jin-Soo Kim Joonwon Lee
Computer Science Division
Korea Advanced Institute of Science and Technology (KAIST)
Daejeon, Korea
{ux,heesn}@calab.kaist.ac.kr {jinsoo,joon}@cs.kaist.ac.kr
ABSTRACT
In NAND flash-based storage systems, an intermediate soft-
ware layer called a flash translation layer (FTL) is usually
employed to hide the erase-before-write characteristics of
NAND flash memory. This paper proposes a novel superblock-
based FTL scheme, which combines a set of adjacent logi-
cal blocks into a superblock. In the proposed FTL scheme,
superblocks are mapped at coarse granularity, while pages
inside the superblock are mapped freely at fine granularity
to any location in several physical blocks. To reduce extra
storage and flash memory operations, the fine-grain map-
ping information is stored in the spare area of NAND flash
memory. This hybrid mapping technique has the flexibility
provided by fine-grain address translation, while reducing
the memory overhead to the level of coarse-grain address
translation. Our experimental results show that the pro-
posed FTL scheme decreases the garbage collection overhead
up to 40% compared to previous FTL schemes.
Categories and Subject Descriptors
D.4.2 [Operating Systems]: Storage Management—Garb age
col lection
General Terms
Management,Measurement,Performance,Design
Keywords
NAND flash memory, flash translation layer(FTL), address
translation
1. INTRODUCTION
∗
This research was supported by the MIC(Ministry of
Information and Communication), Korea, under the
ITRC(Inofrmation Technology Research Center) support
program supervised by the IITA(Institute of Information
Technology Assessment) (IITA-2005-C1090-0502-0031)
Permission to make digital or hard copies of all or part of this work for
personal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that copies
bear this notice and the full citation on the first page. To copy otherwise, to
republish, to post on servers or to redistribute to lists, requires prior specific
permission and/or a fee.
EMSOFT’06, October 22–25, 2006, Seoul, Korea.
Copyright 2006 ACM 1-59593-542-8/06/0010 ...
$5.00.
Many mobile devices, including MP3 players, PDAs (per-
sonal digital assistants), PMPs (portable media players),
high-resolution digital cameras and camcorders, and mo-
bile phones, demand a large-capacity and high-performance
storage system in order to store, retrieve, and process large
multimedia data quickly. In those devices, NAND flash
memory is already becoming one of the most common stor-
age medium because of its versatile features such as non-
volatility, solid-state reliability, low power consumption, shock
resistance, and high cell densities [4, 11].
NAND flash memory, however, has a restriction that a
page, which is the basic unit of read and write operations,
should be erased before being rewritten in the same loca-
tion. This characteristic is sometimes called erase-before-
write. Moreover, the erase operations can only be performed
on a larger block than the page. Therefore, an intermediate
software layer called a flash translation layer (FTL) is usu-
ally employed to hide the limitation of erase-before-write [8,
3]. FTL achieves this by redirecting each write request to an
empty location in NAND flash memory that has been erased
in advance, and by managing an internal mapping table to
record the mapping information from the logical sector num-
ber to the physical location. Although FTL gives an ability
to update the same logical sector transparently without in-
tervention of erase operation, it needs extra flash memory
operations to prepare empty locations and extra storage to
maintain the internal mapping table. The amount of extra
operations and storage required is drastically varied depend-
ing on the employed FTL schemes.
There is trade off between extra storage and extra op-
erations. While coarse-grain address translation lowers the
amount of extra storage, it may cause more extra flash mem-
ory operations to keep up the mapping state regularly. On
the other hand, fine-grain address translation is flexible in
handling of write requests smaller than a block, but demands
more extra storage for managing mapping information. As
the capacity of NAND flash-based storage increases, the ex-
tra storage required by fine-grain address translation actu-
ally imposes a serious cost problem in mass-market products
[9].
In this paper, we propose a novel FTL scheme called su-
perblock FTL scheme for NAND flash memory. In the pro-
posed scheme, a superblock consists of a set of adjacent log-
ical blocks. Superblocks are mapped at coarse granularity,
while pages inside the superblock are mapped freely at fine
granularity to any location in several physical blocks. To re-
duce extra storage and extra flash memory operations, the
fine-grain mapping information is stored in the spare area
161
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