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针对FPGA学习者,主要讲解约束问题,全局约束,偏移约束等等。
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Global Timing Constraints 5 -1
Chapter 5
Global Timing Constraints
Global Timing Constraints 5 -2
Objectives
Objectives
w Apply timing constraints to a simple synchronous
design
w Specify global timing constraints and pin assignments
with the Constraints Editor
After completing this module, you will be able to…
Global Timing Constraints 5 -3
Outline
Outline
w Introduction
w The Period Constraint
w The Offset Constraint
w The Constraints Editor
w Summary
Global Timing Constraints 5 -4
What Effects Do Timing Constraints
What Effects Do Timing Constraints
Have on Your Project?
Have on Your Project?
w The Implementation tools don’t try to find the place and
route that will obtain the best speed
w Instead, the Implementation tools try to meet your
performance expectations
w Performance expectations are communicated with timing
constraints
w Timing Constraints improve the design performance by
placing logic closer together so shorter routing resources
can be used
w Note that when we discuss using the Constraint Editor, we
are referring to the Design Manager Constraints Editor
Global Timing Constraints 5 -5
What Needs Constraining?
What Needs Constraining?
w Internal clock speed for one or more clocks
w I/O speed
w Logic using multi-cycle clocks
w Pin to Pin timing
w Pin Locations & Logic Locations
OUT1
X
Y
Z<0:9>
OUT2
2 Levels of Logic
Clk & CE Speed
I/O Speed
Pin 2 Pin Speed
I/O Speed
Pin
Locations
Pin
Locations
Logic
Locations
1 Level of Logic
QD QD
CLK
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