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C8051F120倍频函数
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2014-07-05
21:53:03
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函数原型:void ClockConfig(void) 入口参数:无 出口参数:无 功能描述:系统时钟的初始化配置,采用PLL倍频22.1184M*4=88.4736M 完全按照芯片手册上的步骤给C8051F120单片机倍频,在我的单片机上倍频成功
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/***********************************************************
时间:20140611
作者:CRJ
函数原型:void ClockConfig(void)
入口参数:无
出口参数:无
功能描述:系统时钟的初始化配置,采用PLL倍频22.1184M*4=88.4736M
************************************************************/
void ClockConfig(void)
{
SFRPAGE = CONFIG_PAGE;
SFRPGCN |= 0x01; //SFR Automatic Paging enabled
OSCXCN = 0x67; //Crystal Oscillator Mode.10 MHz < f ≤ 30 MHz
Delay(6000);
while((OSCXCN&0x80) == 0); //Step 1. Ensure that the reference clock to be used (internal or external) is running and stable.
PLL0CN |= 0x04; //Step 2. Set the PLLSRC bit (PLL0CN.2) to select the desired clock source for the PLL.
SFRPAGE = 0x00;
FLSCL |= 0x30; //Step 3. Program the FLASH read timing bits, FLRT (FLSCL.5-4) to the appropriate value for the new clock rate
SFRPAGE = CONFIG_PAGE;
PLL0CN |= 0x01; //Step 4. Enable power to the PLL by setting PLLPWR (PLL0CN.0) to ‘1’.
PLL0DIV = 0x01; //Step 5. Program the PLL0DIV register to produce the divided reference frequency to the PLL.
PLL0FLT |= 0x01;
PLL0FLT &= 0xF1; //Step 6. Program the PLLLP3-0 bits (PLL0FLT.3-0) to the appropriate range for the divided reference frequency.
PLL0FLT &= 0xCF; //Step 7. Program the PLLICO1-0 bits (PLL0FLT.5-4) to the appropriate range for the PLL output frequency.
PLL0MUL = 0x04; //Step 8. Program the PLL0MUL register to the desired clock multiplication factor.
Delay(6000); //Step 9. Wait at least 5 μs, to provide a fast frequency lock.
PLL0CN |= 0x02; //Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to ‘1’.
while((PLL0CN&0x10)==0); //Step 11. Poll PLLLCK (PLL0CN.4) until it changes from ‘0’ to ‘1’
CLKSEL |= 0x02;
CLKSEL &= 0xFE; //Step 12. Switch the System Clock source to the PLL using the CLKSEL register.
时间:20140611
作者:CRJ
函数原型:void ClockConfig(void)
入口参数:无
出口参数:无
功能描述:系统时钟的初始化配置,采用PLL倍频22.1184M*4=88.4736M
************************************************************/
void ClockConfig(void)
{
SFRPAGE = CONFIG_PAGE;
SFRPGCN |= 0x01; //SFR Automatic Paging enabled
OSCXCN = 0x67; //Crystal Oscillator Mode.10 MHz < f ≤ 30 MHz
Delay(6000);
while((OSCXCN&0x80) == 0); //Step 1. Ensure that the reference clock to be used (internal or external) is running and stable.
PLL0CN |= 0x04; //Step 2. Set the PLLSRC bit (PLL0CN.2) to select the desired clock source for the PLL.
SFRPAGE = 0x00;
FLSCL |= 0x30; //Step 3. Program the FLASH read timing bits, FLRT (FLSCL.5-4) to the appropriate value for the new clock rate
SFRPAGE = CONFIG_PAGE;
PLL0CN |= 0x01; //Step 4. Enable power to the PLL by setting PLLPWR (PLL0CN.0) to ‘1’.
PLL0DIV = 0x01; //Step 5. Program the PLL0DIV register to produce the divided reference frequency to the PLL.
PLL0FLT |= 0x01;
PLL0FLT &= 0xF1; //Step 6. Program the PLLLP3-0 bits (PLL0FLT.3-0) to the appropriate range for the divided reference frequency.
PLL0FLT &= 0xCF; //Step 7. Program the PLLICO1-0 bits (PLL0FLT.5-4) to the appropriate range for the PLL output frequency.
PLL0MUL = 0x04; //Step 8. Program the PLL0MUL register to the desired clock multiplication factor.
Delay(6000); //Step 9. Wait at least 5 μs, to provide a fast frequency lock.
PLL0CN |= 0x02; //Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to ‘1’.
while((PLL0CN&0x10)==0); //Step 11. Poll PLLLCK (PLL0CN.4) until it changes from ‘0’ to ‘1’
CLKSEL |= 0x02;
CLKSEL &= 0xFE; //Step 12. Switch the System Clock source to the PLL using the CLKSEL register.
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