################################################################################
# Vivado (TM) v2020.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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基于BPSK调制解调的卷积编解码的FPGA实现工程源码
共1691个文件
sdb:1112个
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v:57个
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2023-04-03
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基于BPSK调制解调的卷积编解码的FPGA实现工程源码。已经经过测试。 开发软件:Vivado2020.1,Verilog源码。里面有7个.v,5个IP核。可直接下载使用。方案介绍见博客“卷积编解码的FPGA实现(1)”“卷积编解码的FPGA实现(2)”卷积编解码的FPGA实现(3)。
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基于BPSK调制解调的卷积编解码的FPGA实现工程源码 (1691个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 28KB
xsim.ini.bak 28KB
elaborate.bat 2KB
elaborate.bat 1KB
compile.bat 980B
simulate.bat 918B
simulate.bat 900B
compile.bat 830B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
xsim_8.c 2.28MB
xsim_4.c 567KB
xsim_2.c 137KB
fir_2m.coe 8KB
fir_2m.coe 8KB
fir_2m.coe 8KB
fir_2m.coe 8KB
xsim.dbg 75KB
xsim.dbg 24KB
xsim.dbg 13KB
fir_2m.dcp 1.43MB
fir_2m.dcp 1.43MB
fir_2m.dcp 1.43MB
viterbi_0.dcp 933KB
viterbi_0.dcp 933KB
viterbi_0.dcp 923KB
viterbi_0.dcp 923KB
dds_cos.dcp 47KB
dds_cos.dcp 47KB
dds_cos.dcp 46KB
mult_8_8.dcp 24KB
mult_8_8.dcp 24KB
mult_8_8.dcp 24KB
top.dcp 24KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 653B
compile.do 629B
compile.do 597B
compile.do 587B
simulate.do 516B
simulate.do 509B
simulate.do 509B
elaborate.do 391B
simulate.do 304B
simulate.do 299B
simulate.do 299B
simulate.do 188B
simulate.do 184B
elaborate.do 179B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
xsimk.exe 8.71MB
xsimk.exe 1.75MB
xsimk.exe 744KB
run.f 1KB
run.f 1KB
run.f 449B
run.f 433B
fir_2m.h 5KB
.xsim_webtallk.info 65B
.xsim_webtallk.info 64B
.xsim_webtallk.info 64B
xsim.ini 28KB
xsim.ini 28KB
xsim.ini 28KB
xsim.ini 28KB
xsimSettings.ini 1KB
xsimSettings.ini 1KB
xsimSettings.ini 1KB
webtalk_14596.backup.jou 877B
webtalk.jou 876B
webtalk_4256.backup.jou 843B
webtalk_14572.backup.jou 842B
webtalk_6636.backup.jou 841B
webtalk_7584.backup.jou 841B
webtalk_6360.backup.jou 841B
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