E28F128J3A-150手册资源-CSDN文库

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### E28F128J3A-150 芯片手册知识点解析 #### 一、产品概述 **E28F128J3A-150**是一款采用Intel 0.25微米技术制造的StrataFlash存储器，主要面向高密度、低成本的应用市场。该产品提供了128Mbit（16MB）、64Mbit以及32Mbit三种不同的容量选择，以满足不同应用场景的需求。 #### 二、产品特性与优势 ##### 1. 高密度与紧凑空间 - **高密度**: 利用Intel先进的0.25微米两比特单元技术，该系列存储器能够在相同的空间内提供双倍的数据容量。 - **节省空间**: 这种高密度设计有助于减少电路板的空间占用，特别适合于那些空间受限的应用环境。 ##### 2. 高速接口与性能 - **异步页面模式读取**: 支持快速的异步页面模式读取功能，确保了高效的数据传输速率。 - **读取访问时间**: - 32Mbit: 110/25ns - 64Mbit: 120/25ns - 128Mbit: 150/25ns - **这些读取时间**表明即使在较高密度下也能保持良好的性能表现。 ##### 3. 成本效益 - **最低成本每比特**: 通过优化的设计和制造工艺，使得这款存储器能够提供市场上最低的成本每比特价格。 - **支持代码和数据存储**: 可以同时用于存储程序代码和运行时数据，从而减少了对于额外存储解决方案的需求。 ##### 4. 易于迁移与升级 - **FlashFile™内存家族引脚布局**: 使用相同的引脚布局，便于从现有的Word-Wide FlashFile存储器或第一代StrataFlash存储器设备进行平滑迁移。 - **软件兼容性**: 提供了向前兼容的软件支持，利用通用闪存接口(CFI)和可扩展命令集(SCS)，方便客户在未来密度升级时仍能保持良好的写入性能。 #### 三、技术规格 ##### 1. 工作电压 - **操作电压范围**: 2.7V至3.6V VCC，这意味着可以在较宽的电压范围内正常工作。 ##### 2. 架构特点 - **高密度对称阻塞架构**: - 128Mbit: 128个128K字节擦除块 - 64Mbit: 64个128K字节擦除块 - 32Mbit: 32个128K字节擦除块 - 这种架构设计使得每个擦除块具有相同大小，有利于提高擦写操作的效率。 ##### 3. 数据保护特性 - **128位保护寄存器**: - 包含64位唯一设备标识符 - 包含64位用户可编程一次性编程(OTP)单元 - 这些特性为设备提供了基本的安全保障，如防止非法访问和数据篡改等。 ##### 4. 增强型数据保护功能 - 除了基本的数据保护机制外，还提供了其他增强型的数据保护功能，虽然具体细节没有详细说明，但可以推测包括但不限于错误校验与纠正(ECC)机制等。 #### 四、适用场景 - **网络通信**: 适用于路由器、交换机等网络设备中的固件存储。 - **电信领域**: 如基站控制器中的数据存储。 - **数字家庭娱乐**: 数字机顶盒、音频录制设备和数字成像系统等。 - **工业控制**: 控制器、自动化系统等需要可靠存储解决方案的应用场景。 #### 五、总结 E28F128J3A-150作为一款基于Intel StrataFlash技术的存储器，不仅提供了高密度和高性能的优势，还在成本效益、易用性和数据安全性方面表现出色。无论是对于硬件设计者还是最终用户而言，都是一个非常有吸引力的选择。

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3 Volt Intel

StrataFlash™ Memory

28F128J3A, 28F640J3A, 28F320J3A (x8/x16)

Preliminary Datasheet

Product Features

Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel

StrataFlash™ memory products provide 2X the bits in 1X the space, with new features for mainstream

performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring

reliable, two-bit-per-cell storage technology to the flash market segment.

Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices,

support for code and data storage, and easy migration to future devices.

Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash

memory

devices take advantage of over one billion units of manufacturing experience since 1987. As a

result, Intel StrataFlash components are ideal for code and data applications where high density and low

cost are required. Examples include networking, telecommunications, digital set top boxes, audio

recording, and digital imaging.

By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design

migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation

Intel StrataFlash memory (28F640J5 and 28F320J5) devices.

Intel StrataFlash memory components deliver a new generation of forward-compatible software support.

By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take

advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.

Manufactured on Intel

0.25 micron ETOX™ VI process technology, Intel StrataFlash memory provides

the highest levels of quality and reliability.

■ High-Density Symmetrically-Blocked

Architecture

—128 128-Kbyte Erase Blocks (128 M)

—64 128-Kbyte Erase Blocks (64 M)

—32 128-Kbyte Erase Blocks (32 M)

■ High Performance Interface Asynchronous

Page Mode Reads

—110/25 ns Read Access Time (32 M)

—120/25 ns Read Access Time (64 M)

—150/25 ns Read Access Time (128 M)

■ 2.7 V–3.6 V V

Operation

■ 128-bit Protection Register

—64-bit Unique Device Identifier

—64-bit User Programmable OTP Cells

■ Enhanced Data Protection Features

Absolute Protection with V

PEN

= GND

—Flexible Block Locking

—Block Erase/Program Lockout during

Power Transitions

■ Packaging

—56-Lead TSOP Package

—64-Ball Intel

Easy BGA Package

■ Cross-Compatible Command Support Intel

Basic Command Set

—Common Flash Interface

—Scalable Command Set

■ 32-Byte Write Buffer

—6 µs per Byte Effective Programming

Time

■ 12.8M Total Min. Erase Cycles (128 Mbit)

6.4M Total Min. Erase Cycles (64 Mbit)

3.2M Total Min. Erase Cycles (32 Mbit)

—100K Minimum Erase Cycles per Block

■ Automation Suspend Options

—Block Erase Suspend to Read

—Block Erase Suspend to Program

—Program Suspend to Read

■ 0.25 µ Intel

StrataFlash™ Memory

Technology

Order Number: 290667-008

April 2001

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Preliminary iii

28F128J3A, 28F640J3A, 28F320J3A

Contents

1.0 Product Overview.......................................................................................................1

2.0 Principles of Operation............................................................................................6

2.1 Data Protection......................................................................................................6

3.0 Bus Operations...........................................................................................................7

3.1 Read......................................................................................................................8

3.2 Output Disable.......................................................................................................8

3.3 Standby .................................................................................................................8

3.4 Reset/Power-Down ...............................................................................................8

3.5 Read Query...........................................................................................................9

3.6 Read Identifier Codes............................................................................................9

3.7 Write......................................................................................................................9

4.0 Command Definitions...............................................................................................9

4.1 Read Array Command.........................................................................................13

4.2 Read Query Mode Command .............................................................................13

4.2.1 Query Structure Output ..........................................................................13

4.2.2 Query Structure Overview ......................................................................14

4.2.3 Block Status Register.............................................................................15

4.2.4 CFI Query Identification String ...............................................................15

4.2.5 System Interface Information .................................................................16

4.2.6 Device Geometry Definition....................................................................17

4.2.7 Primary-Vendor Specific Extended Query Table....................................18

4.3 Read Identifier Codes Command........................................................................19

4.4 Read Status Register Command.........................................................................20

4.5 Clear Status Register Command.........................................................................22

4.6 Block Erase Command........................................................................................22

4.7 Block Erase Suspend Command ........................................................................22

4.8 Write to Buffer Command....................................................................................23

4.9 Byte/Word Program Commands .........................................................................24

4.10 Program Suspend Command..............................................................................24

4.11 Set Read Configuration Command .....................................................................24

4.11.1 Read Configuration ................................................................................25

4.12 Configuration Command .....................................................................................25

4.13 Set Block Lock-Bit Commands............................................................................26

4.14 Clear Block Lock-Bits Command.........................................................................27

4.15 Protection Register Program Command .............................................................27

4.15.1 Reading the Protection Register ............................................................27

4.15.2 Programming the Protection Register ....................................................27

4.15.3 Locking the Protection Register .............................................................28

5.0 Design Considerations ..........................................................................................38

5.1 Three-Line Output Control...................................................................................38

5.2 STS and Block Erase, Program, and Lock-Bit Configuration Polling ..................38

5.3 Power Supply Decoupling ...................................................................................38

5.4 Input Signal Transitions - Reducing Overshoots and Undershoots When Using

Preliminary v

28F128J3A, 28F640J3A, 28F320J3A

Revision History

Date of Revision Version Description

07/07/99 -001 Original Version

08/03/99 -002 A

–A

indicated on block diagram

09/07/99 -003 Changed Minimum Block Erase time,I

, I

, Page Mode and Byte

Mode currents. Modified RP# on AC Waveform for Write Operations

12/16/99 -004 Changed Block Erase time and t

AVWH

Removed all references to 5 V I/O operation

Corrected Ordering Information, Valid Combinations entries

Changed Min program time to 211 µs

Added DU to Lead Descriptions table

Changed Chip Scale Package to Ball Grid Array Package

Changed default read mode to page mode

Removed erase queuing from Figure 10, Block Erase Flowchart

03/16/00 -005 Added Program Max time

Added Erase Max time

Added Max page mode read current

Moved tables to correspond with sections

Fixed typographical errors in ordering information and DC parameter

table

Removed V

CCQ1

setting and changed V

CCQ2/3

to V

CCQ1/2

Added recommended resister value for STS pin

Change operation temperature range

Removed note that rp# could go to 14 V

Removed V

of 0.45 V

Removed V

of 2.4 V

Updated I

CCR

Typ values

Added Max lock-bit program and lock times

Added note on max measurements

06/26/00 -006 Updated cover sheet statement of 700 million units to one billion.

Corrected Table 10 to show correct maximum program times.

Corrected error in Max block program time in section 6.7

Corrected typical erase time in section 6.7

2/15/01 -007 Updated cover page to reflect 100K minimum erase cycles.

Updated cover page to reflect 110 ns 32M read speed.

Removed Set Read Configuration command from Table 4.

Updated Table 8 to reflect reserved bits are 1-7; not 2-7.

Updated Table 16 bit 2 definition from R to PSS.

Changed V

PENLK

Max voltage from 0.8 V to 2.0 V, Section 6.4, DC

Characteristics

Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Sec-

tion 6.5, AC Characteristics–Read-Only Operations

(1,2)

Updated write parameter W13 (t

WHRL

) from 90 ns to 500 ns, Section

6.6, AC Characteristics–Write Operations

Updated Max. Program Suspend Latency W16 (t

WHRH1

) from 30 to 75

µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Per-

formance

(1,2,3)

04/13/01 -008 Revised Section 7.0, Ordering Information

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