6678emif例程

/* ============================================================================ * Copyright (c) Texas Instruments Inc 2011 * * Use of this software is controlled by the terms and conditions found in the * license agreement under which this software has been supplied. * =========================================================================== */ /** ============================================================================ example for SRIO configuration and transfer driver on Keystone DSP * ============================================================================= * Revision History * =============== * 10-June-2011 Brighton file created * 13-June-2011 Zhan update * =============================================================================*/ #include "csl_srioAux.h" #include "Keystone_SRIO_init_drv.h" #include "KeyStone_Navigator_init_drv.h" CSL_SrioRegs * srioRegs = (CSL_SrioRegs *)CSL_SRIO_CONFIG_REGS; SerdesRegs * srioSerdesRegs; /*enable globally used blocks including MMR block in SRIO*/ void Keystone_SRIO_GlobalEnable(void) { srioRegs->RIO_GBL_EN = 1; srioRegs->BLOCK_ENABLE_STATUS[0].RIO_BLK_EN= 1; //MMR_EN //wait for enable completion while(0x3 != (srioRegs->RIO_GBL_EN_STAT&0x3)); } /*Enable SRIO blocks*/ void Keystone_SRIO_enable_blocks( SRIO_Block_Enable * blockEn) { srioRegs->BLOCK_ENABLE_STATUS[5].RIO_BLK_EN= blockEn->bBLK5_8_Port_Datapath_EN[0]; srioRegs->BLOCK_ENABLE_STATUS[6].RIO_BLK_EN= blockEn->bBLK5_8_Port_Datapath_EN[1]; srioRegs->BLOCK_ENABLE_STATUS[7].RIO_BLK_EN= blockEn->bBLK5_8_Port_Datapath_EN[2]; srioRegs->BLOCK_ENABLE_STATUS[8].RIO_BLK_EN= blockEn->bBLK5_8_Port_Datapath_EN[3]; srioRegs->BLOCK_ENABLE_STATUS[1].RIO_BLK_EN= blockEn->bBLK1_LSU_EN ; srioRegs->BLOCK_ENABLE_STATUS[2].RIO_BLK_EN= blockEn->bBLK2_MAU_EN ; srioRegs->BLOCK_ENABLE_STATUS[3].RIO_BLK_EN= blockEn->bBLK3_TXU_EN ; srioRegs->BLOCK_ENABLE_STATUS[4].RIO_BLK_EN= blockEn->bBLK4_RXU_EN ; while(srioRegs->BLOCK_ENABLE_STATUS[5].RIO_BLK_EN_STAT != blockEn->bBLK5_8_Port_Datapath_EN[0]); while(srioRegs->BLOCK_ENABLE_STATUS[6].RIO_BLK_EN_STAT != blockEn->bBLK5_8_Port_Datapath_EN[1]); while(srioRegs->BLOCK_ENABLE_STATUS[7].RIO_BLK_EN_STAT != blockEn->bBLK5_8_Port_Datapath_EN[2]); while(srioRegs->BLOCK_ENABLE_STATUS[8].RIO_BLK_EN_STAT != blockEn->bBLK5_8_Port_Datapath_EN[3]); while(srioRegs->BLOCK_ENABLE_STATUS[1].RIO_BLK_EN_STAT != blockEn->bBLK1_LSU_EN ); while(srioRegs->BLOCK_ENABLE_STATUS[2].RIO_BLK_EN_STAT != blockEn->bBLK2_MAU_EN ); while(srioRegs->BLOCK_ENABLE_STATUS[3].RIO_BLK_EN_STAT != blockEn->bBLK3_TXU_EN ); while(srioRegs->BLOCK_ENABLE_STATUS[4].RIO_BLK_EN_STAT != blockEn->bBLK4_RXU_EN ); } /*Disable all SRIO blocks*/ void Keystone_SRIO_disable_all_blocks() { srioRegs->BLOCK_ENABLE_STATUS[1].RIO_BLK_EN= 0; //LSU_EN srioRegs->BLOCK_ENABLE_STATUS[2].RIO_BLK_EN= 0; //MAU_EN srioRegs->BLOCK_ENABLE_STATUS[3].RIO_BLK_EN= 0; //TXU_EN srioRegs->BLOCK_ENABLE_STATUS[4].RIO_BLK_EN= 0; //RXU_EN srioRegs->BLOCK_ENABLE_STATUS[5].RIO_BLK_EN= 0; //PORT0_EN srioRegs->BLOCK_ENABLE_STATUS[6].RIO_BLK_EN= 0; //PORT1_EN srioRegs->BLOCK_ENABLE_STATUS[7].RIO_BLK_EN= 0; //PORT2_EN srioRegs->BLOCK_ENABLE_STATUS[8].RIO_BLK_EN= 0; //PORT3_EN srioRegs->BLOCK_ENABLE_STATUS[0].RIO_BLK_EN= 0; //MMR_EN srioRegs->RIO_GBL_EN = 0; //wait for disable completion while(srioRegs->RIO_GBL_EN_STAT&1); } /*soft shutdown and reset SRIO*/ void Keystone_SRIO_soft_reset() { int i, j, k; /*shut down TXU/RXU transaction*/ for(i=0; i<SRIO_PKTDMA_MAX_CH_NUM; i++) { KeyStone_pktDma_RxCh_teardown(srioDmaRxChCfgRegs, i); KeyStone_pktDma_TxCh_teardown(srioDmaTxChCfgRegs, i); } for(i= 0; i<SRIO_MAX_LSU_NUM ; i++) { /*flash LSU transfer for all Source ID*/ for(j=0; j< SRIO_MAX_DEVICEID_NUM; j++) { srioRegs->LSU_CMD[i].RIO_LSU_REG6 = CSL_SRIO_RIO_LSU_REG6_FLUSH_MASK| /*flash*/ (j<<CSL_SRIO_RIO_LSU_REG6_SCRID_MAP_SHIFT); /*This can take more than one cycle to do the flush. wait for a while*/ for(k=0; k< 100; k++) asm(" nop 5"); } } /*disable the PEREN bit of the PCR register to stop all new logical layer transactions.*/ srioRegs->RIO_PCR &= (~CSL_SRIO_RIO_PCR_PEREN_MASK); /*Wait one second to finish any current DMA transfer.*/ for(i=0; i< 100000000; i++) asm(" nop 5"); //reset all logic blocks in SRIO Keystone_SRIO_disable_all_blocks(); //disable Serdes Keystone_Serdes_disable(srioSerdesRegs, 4); //disable SRIO through PSC Keystone_disable_PSC_module(CSL_PSC_PD_SRIO, CSL_PSC_LPSC_SRIO); Keystone_disable_PSC_Power_Domain(CSL_PSC_PD_SRIO); } /*configure SRIO 1x 2x or 4x path mode*/ void Keystone_SRIO_set_1x2x4x_Path( SRIO_1x2x4x_Path_Control srio_1x2x4x_path_control) { /*This register is a global register, even though it can be accessed from any port. So you do not need to program from each port, it is basically a single register. The PathID is a RO value, that is driven by the H/W. You cannot modify it*/ srioRegs->RIO_PLM[0].RIO_PLM_SP_PATH_CTL= (srioRegs->RIO_PLM[0].RIO_PLM_SP_PATH_CTL&(~SRIO_1x2x4x_PATH_CONTROL_MASK))| srio_1x2x4x_path_control; } /*SRIO timeout configuration in microsecond*/ void Keystone_SRIO_Timeout_Config(SRIO_Config * srio_cfg, Uint32 logicalRepsonseTimeout_us, Uint32 physicalPortTimeout_us, Uint32 linkInitSilenceTimeout_us) { Uint32 uiTimeout, uiMaxTimeout; /*PRESCALAR_SELECT is used to divide VBUSM clock(normally 333 to 400MHz, here use 350MHz), (VBUS_M clock)/(PRESCALAR_SELECT+1), to get about 50MHz clock with about 20ns period.*/ srioRegs->RIO_PER_SET_CNTL= (srioRegs->RIO_PER_SET_CNTL &(~CSL_SRIO_RIO_PER_SET_CNTL_PRESCALER_SELECT_MASK)) |((350/50-1)<<CSL_SRIO_RIO_PER_SET_CNTL_PRESCALER_SELECT_SHIFT); /*logical layer response timeout logicalRepsonseTimeout = 15 x (scaled VBUS_M clock period) x TIMEOUT_VALUE), TIMEOUT_VALUE = logicalRepsonseTimeout/(scaled VBUS_M clock period)/15 */ uiTimeout= logicalRepsonseTimeout_us*1000/20/15; uiMaxTimeout=CSL_SRIO_RIO_SP_RT_CTL_TVAL_MASK >>CSL_SRIO_RIO_SP_RT_CTL_TVAL_SHIFT; if(uiTimeout>uiMaxTimeout) uiTimeout= uiMaxTimeout; if(0==uiTimeout) uiTimeout= 1; srioRegs->RIO_SP_RT_CTL= uiTimeout<<CSL_SRIO_RIO_SP_RT_CTL_TVAL_SHIFT; /*PRESCALAR_SRV_CLK is used to divide SRIO reference clock to get about 10MHz SRV_CLK with about 100ns period. */ srioRegs->RIO_PRESCALAR_SRV_CLK= (Uint32)srio_cfg->serdes_cfg->commonSetup.inputRefClock_MHz/10; /*physical layer response timeout. physicalPortTimeout = SRV_CLK period * TIMEOUT_VALUE * 3, TIMEOUT_VALUE = physicalPortTimeout/SRV_CLK period/3 */ uiTimeout= physicalPortTimeout_us*1000/100/3; uiMaxTimeout=CSL_SRIO_RIO_SP_LT_CTL_TVAL_MASK >>CSL_SRIO_RIO_SP_LT_CTL_TVAL_SHIFT; if(uiTimeout>uiMaxTimeout) uiTimeout= uiMaxTimeout; if(0==uiTimeout) uiTimeout= 1; srioRegs->RIO_SP_LT_CTL= uiTimeout<<CSL_SRIO_RIO_SP_LT_CTL_TVAL_SHIFT; /*port silence timeout The SRIO starts in the SILENT state. The link output driver is disabled to force the link partner to initialize regardless of its current state. The duration of the SILENT state is controlled by the silence_timer. The duration must be long enough to ensure that the link partner detects the silence (as a loss of lane_sync) and is forced to initialize but short enough that it is readily distinguished from a link break. linkInitSilenceTimeout is SRV_CLK period X 410 X SILENCE_TIMER, SILENCE_TIMER= linkInitSilenceTimeout/SRV_CLK period/410*/ uiTimeout= linkInitSilenceTimeout_us*1000/100/410; uiMaxTimeout=CSL_SRIO_RIO_PLM_SP_SILENCE_TIMER_SILENCE_TIMER_MASK >>CSL_SRIO_RIO_PLM_SP_SILENCE_TIMER_SILENCE_TIMER_SHIFT; if(uiTimeout>uiMaxTimeout) uiTimeout= uiMaxTimeout; if(0==uiTimeout) uiTimeout= 1; uiTimeout= uiTime