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AT25DF041A - datasheet
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ATMEL 串行外接Flash AT25DF041A datasheet
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Features
• Single 2.3V - 3.6V or 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
• 70 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature
– One 16-Kbyte Top Sector
– Two 8-Kbyte Sectors
– One 32-Kbyte Sector
– Seven 64-Kbyte Sectors
• Hardware Controlled Locking of Protected Sectors via WP pin
• Flexible Programming Options
– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability
• Fast Program and Erase Times
– 1.2 ms Typical Page Program (256 Bytes) Time
– 50 ms Typical 4-Kbyte Block Erase Time
– 250 ms Typical 32-Kbyte Block Erase Time
– 400 ms Typical 64-Kbyte Block Erase Time
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 5 mA Active Read Current (Typical)
– 15 µA Deep Power-down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil Wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
1. Description
The AT25DF041A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DF041A, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
4-megabit
2.3-volt or
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25DF041A
3668D–DFLASH–9/08
2
3668D–DFLASH–9/08
AT25DF041A
The physical sectoring and the erase block sizes of the AT25DF041A have been optimized to
meet the needs of today’s code and data storage applications. By optimizing the size of the
physical sectors and erase blocks, the memory space can be used much more efficiently.
Because certain code modules and data storage segments must reside by themselves in their
own protected sectors, the wasted and unused memory space that occurs with large sectored
and large block erase Flash memory devices can be greatly reduced. This increased memory
space efficiency allows additional code routines and data storage segments to be added while
still maintaining the same overall device density.
The AT25DF041A also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT25DF041A incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
Specifically designed for use in 2.5-volt or 3-volt systems, the AT25DF041A supports read, pro-
gram, and erase operations with a supply voltage range of 2.3V to 3.6V or 2.7V to 3.6V. No
separate voltage is required for programming and erasing.
3
3668D–DFLASH–9/08
AT25DF041A
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol Name and Function
Asserted
State Type
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS
pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
Low Input
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
Input
SI
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
Input
SO
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
Output
WP
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
section “Protection Commands and Features” on page 15 for more details on protection features
and the WP pin.
The WP
pin is internally pulled-high and may be left floating if hardware-controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
CC
whenever possible.
Low Input
HOLD
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS
pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold”
on page 30 for additional details on the Hold operation.
The HOLD
pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD
pin also be externally connected to V
CC
whenever
possible.
Low Input
V
CC
DEVICE POWER SUPPLY: The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
Power
GND
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
Power
Figure 2-1. 8-SOIC Top View Figure 2-2. 8-UDFN Top View
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
4
3668D–DFLASH–9/08
AT25DF041A
3. Block Diagram
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF041A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
FLASH
MEMORY
ARRAY
Y-GATING
CS
SCK
SO
SI
Y-DECODER
ADDRESS LATCH
X-DECODER
I/O BUFFERS
AND LATCHES
CONTROL AND
PROTECTION LOGIC
SRAM
DATA BUFFER
WP
INTERFACE
CONTROL
AND
LOGIC
5
3668D–DFLASH–9/08
AT25DF041A
Figure 4-1. Memory Architecture Diagram
4KB
07FFFFh – 07F000h
256 Bytes
07FFFFh – 07FF00h
4KB
07EFFFh – 07E000h
256 Bytes
07FEFFh – 07FE00h
4KB
07DFFFh – 07D000h
256 Bytes
07FDFFh – 07FD00h
4KB
07CFFFh – 07C000h
256 Bytes
07FCFFh – 07FC00h
4KB
07BFFFh – 07B000h
256 Bytes
07FBFFh – 07FB00h
4KB
07AFFFh – 07A000h
256 Bytes
07FAFFh – 07FA00h
4KB
079FFFh – 079000h
256 Bytes
07F9FFh – 07F900h
4KB
078FFFh – 078000h
256 Bytes
07F8FFh – 07F800h
4KB
077FFFh – 077000h
256 Bytes
07F7FFh – 07F700h
4KB
076FFFh – 076000h
256 Bytes
07F6FFh – 07F600h
4KB
075FFFh – 075000h
256 Bytes
07F5FFh – 07F500h
4KB
074FFFh – 074000h
256 Bytes
07F4FFh – 07F400h
4KB
073FFFh – 073000h
256 Bytes
07F3FFh – 07F300h
4KB
072FFFh – 072000h
256 Bytes
07F2FFh – 07F200h
4KB
071FFFh – 071000h
256 Bytes
07F1FFh – 07F100h
4KB
070FFFh – 070000h
256 Bytes
07F0FFh – 07F000h
4KB
06FFFFh – 06F000h
256 Bytes
07EFFFh – 07EF00h
4KB
06EFFFh – 06E000h
256 Bytes
07EEFFh – 07EE00h
4KB
06DFFFh – 06D000h
256 Bytes
07EDFFh – 07ED00h
4KB
06CFFFh – 06C000h
256 Bytes
07ECFFh – 07EC00h
4KB
06BFFFh – 06B000h
256 Bytes
07EBFFh – 07EB00h
4KB
06AFFFh – 06A000h
256 Bytes
07EAFFh – 07EA00h
4KB
069FFFh – 069000h
256 Bytes
07E9FFh – 07E900h
4KB
068FFFh – 068000h
256 Bytes
07E8FFh – 07E800h
4KB
067FFFh – 067000h
4KB
066FFFh – 066000h
4KB
065FFFh – 065000h
4KB
064FFFh – 064000h
256 Bytes
0017FFh – 001700h
4KB
063FFFh – 063000h
256 Bytes
0016FFh – 001600h
4KB
062FFFh – 062000h
256 Bytes
0015FFh – 001500h
4KB
061FFFh – 061000h
256 Bytes
0014FFh – 001400h
4KB
060FFFh – 060000h
256 Bytes
0013FFh – 001300h
256 Bytes
0012FFh – 001200h
256 Bytes
0011FFh – 001100h
256 Bytes
0010FFh – 001000h
4KB
00FFFFh – 00F000h
256 Bytes
000FFFh – 000F00h
4KB
00EFFFh – 00E000h
256 Bytes
000EFFh – 000E00h
4KB
00DFFFh – 00D000h
256 Bytes
000DFFh – 000D00h
4KB
00CFFFh – 00C000h
256 Bytes
000CFFh – 000C00h
4KB
00BFFFh – 00B000h
256 Bytes
000BFFh – 000B00h
4KB
00AFFFh – 00A000h
256 Bytes
000AFFh – 000A00h
4KB
009FFFh – 009000h
256 Bytes
0009FFh – 000900h
4KB
008FFFh – 008000h
256 Bytes
0008FFh – 000800h
4KB
007FFFh – 007000h
256 Bytes
0007FFh – 000700h
4KB
006FFFh – 006000h
256 Bytes
0006FFh – 000600h
4KB
005FFFh – 005000h
256 Bytes
0005FFh – 000500h
4KB
004FFFh – 004000h
256 Bytes
0004FFh – 000400h
4KB
003FFFh – 003000h
256 Bytes
0003FFh – 000300h
4KB
002FFFh – 002000h
256 Bytes
0002FFh – 000200h
4KB
001FFFh – 001000h
256 Bytes
0001FFh – 000100h
4KB
000FFFh – 000000h
256 Bytes
0000FFh – 000000h
64KB
(Sector 0)
32KB
32KB
• • •
64KB
32KB
32KB
• • •
• • •
• • •
64KB
32KB
32KB
• • •
64KB
(Sector 6)
64KB
16KB
(Sector 10)
8KB
(Sector 9)
8KB
(Sector 8)
32KB
(Sector 7)
Internal Sectoring fo
r
64KB 32KB 4KB 1-256 Byte
Sector Protection Block Erase Block Erase Block ErasePage Program
Function (D8h Command) (52h Command) (20h Command) (02h Command)
Block Erase Detail Page Program Detail
Page AddressBlock Address
RangeRange
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